Question

vhdl 全局变量初始化问题

用max+plusII 编VHDL程序，用到全局变量且需要对其初始化，直接在声明时初始化没有作用。自己写了个初始化的进程，编译时报错unresolved signal is multiply driven。如何才能解决这个初始化问题？本人初学者，还请不吝赐教！
程序如下

library ieee;
use ieee.std_logic_1164.all;

entity one3 is
port(x1,x2,x3: in std_logic_vector(2 downto 0);
res: in std_logic;
out0 : out integer range 0 to 3;
xuhao1,xuhao2: out integer range 0 to 3;
a,b : out std_logic_vector(1 downto 0);
en : out std_logic);
end one3;

architecture beha of one3 is
signal j: integer range 0 to 1 ;
signal en1: std_logic_vector(2 downto 0) ;
begin
process(res)-------------我编的初始化化进程
begin
en1<="111";
out0<=0;
j<=0;
end process;-----------------

process(x3,en1)
begin
if x3=en1 then

if( en1="111") then
case x1 is---
when "001"=>en1(0)<='0';
xuhao1<=2;
xuhao2<=3;
out0<=1;
when "010"=>en1(1)<='0';
xuhao1<=1;
xuhao2<=3;
out0<=2;
when "100"=>en1(2)<='0';
xuhao1<=1;
xuhao2<=2;
out0<=3;
when "011"=>en1(2)<='0';
xuhao1<=1;
xuhao2<=2;
out0<=3;
when "101"=>en1(1)<='0';
xuhao1<=1;
xuhao2<=3;
out0<=2;
when "110"=>en1(0)<='0';
xuhao1<=2;
xuhao2<=3;
out0<=1;

when others=>out0<=0;
end case;
else
checkloop: for i in 0 to 2 loop
if en1(i)='1' then
a(j)<=x1(i);
b(j)<=x2(i);
j<=j+1;
end if;
end loop checkloop;
en<='1';
end if;

end if;

end process;
end beha;

Answer 1

在VHDL里面，每个进程都是并行的，不是按顺序的，你在两个进程里面同时对信号赋值当然是错误的。。你可以这样初始化
1、signal en1:std_logic_vector(2 downt 0):="111";
2、一般程序里面都有加个复位来初始化，
if reset='1' then
en1<="111";