Question

VHDL中这有个错误，怎么改正？

Library Ieee;
Use Ieee.std_logic_1164.all;
Entity a Is
port(u_d,cp:In Std_Logic;
q2,q1,q0:Out Std_Logic);
End a;
Architecture b Of a Is
signal t0,t1,t2:Std_logic;
Begin
process(u_d,cp)
Begin
if u_d='1' then
t1 <= q0;
t2 <= q1 and q0;
elsif u_d='0' then
t1 <= not q0;
t2 <= not q1 and not q0;
end if;
if cp'EVENT AND cp='1'and (q2 /= '1' and q1 /= '0' and q0 /= '1') then
q0 <= not q0;
if t1 = '1' then
q1 <= not q1;
end if;
if t2 = '1' then
q2 <= not q2;
end if;
end if;
end process;
end b;

Error (10309): VHDL Interface Declaration error in a.vhd(13): interface object "q0" of mode out cannot be read. Change object mode to buffer.

Answer 1

q0:Out Std_Logicg改成q0:buffer Std_Logicg。因为在t1 <= q0;等中，作为Out的洞做和q0不允纳盯胡余许出现在右边。