Question

本人是初学者，为什么这段VHDL程序会出现这种错误

entity and3 is
port (a,b:in bit;
y:out bit);
end entity and3;
architecture one of and3 is
begin
y<=a and b;
end
错误如下
Error (10522): VHDL Syntax error at /and3.vhd(8): experienced unexpected end-of-file ; expecting ";", or an identifier, or "architecture"
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 182 megabytes
Error: Processing ended: Fri Nov 11 11:07:04 2011
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 1 warning

Answer 1

我把你这个程序复制到 MAXPLUSII里面做了一下，只是发现end后面少了一个“；”没别的问题了。还有就是检查下你保存这个文本时的名字是不是and3.vhd，然后有没有设置为当前工程（File→Project→Set project to current file）.完毕

Answer 2

VHDL的语法还要多学习了
architecture one of and3 is
begin
y<=a and b;
end
应该是 end one;最后要分号的

Answer 3

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity and3 is
port (a,b:in bit;
y:out bit
);
end and3;------------------------------
architecture one of and3 is
begin
y<=a and b;
end one;----------------------------------

追问

照着上面写了，出现了这错误Error: Top-level design entity "AND2" is undefined。AND2是我那个project的名称，这个有冲突吗

追答

实体名必须和工程名一致，
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity and2 is-------------------------
port (a,b:in bit;
y:out bit
);
end and2;------------------------------
architecture one of and2 is------------------------
begin
y<=a and b;
end one;
把实体名改成and2就行了

Answer 4

end后面少个分号