Question

VHDL语言编写4MHz分频产生1Hz..要能在QuartusII中用的..

Answer 1

不用这么复杂，结构体只要5行搞定

Answer 2

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fenpin IS
PORT(A:IN STD_LOGIC;
Q:OUT STD_LOGIC);
END FENPIN;

ARCHITECTURE ONE OF fenpin IS
SIGNAL B:integer range 0 to 1999999;
SIGNAL C:STD_LOGIC;
SIGNAL d:STD_LOGIC;

BEGIN
PROCESS(A)
BEGIN
IF A'EVENT AND A='1' THEN
IF B=1999999 THEN
B<=0;
C<='1';
ELSE
B<=B+1;
C<='0';
END IF;
END IF;
END PROCESS;

PROCESS(c)
BEGIN
IF C'EVENT AND C='1' THEN
d<=NOT d;
END IF;
END PROCESS;
q<=d;
END ONE;