Question

VHDL程序错误分析 仿真没有输出端口

该VHDL实现将时间输出，其中flash和position用于调时时的显示，可以忽略。下段程序编译成功，在波形仿真时却无法导入输出端口，这是怎么回事？谢谢

library ieee;
use ieee.std_logic_1164.all;

entity seg is

port
(
clk : in std_logic;
hourh : in integer range 0 to 2;
hourl : in integer range 0 to 9;
minuteh : in integer range 0 to 5;
minutel : in integer range 0 to 9;
secondh : in integer range 0 to 5;
secondl : in integer range 0 to 9;
position: in integer range 0 to 5;
flash : in std_logic;
duan : out std_logic_vector(7 to 0);
wei : out std_logic_vector(5 to 0)
);

end seg;

architecture a of seg is

signal i: integer range 0 to 7;
signal dis: std_logic_vector(7 downto 0);
signal num: integer range 0 to 9;
signal cat: std_logic_vector(5 downto 0);
begin
p0:
process(clk)
begin
if(rising_edge(clk)) then
i <= i+1;
end if;
end process;

p1:
process(i)
begin
case i is
when 0=>cat<="111110"; num<=secondl;
when 1=>cat<="111101"; num<=secondh;
when 2=>cat<="111011"; num<=minutel;
when 3=>cat<="110111"; num<=minuteh;
when 4=>cat<="101111"; num<=hourl;
when 5=>cat<="011111"; num<=hourh;
when others=>cat<="000000";
end case;

case num is
when 0=>dis<="11111100";
when 1=>dis<="01100000";
when 2=>dis<="11011010";
when 3=>dis<="11110010";
when 4=>dis<="01100110";
when 5=>dis<="10110110";
when 6=>dis<="10111110";
when 7=>dis<="11100000";
when 8=>dis<="11111110";
when 9=>dis<="11110110";
end case;

if (flash='0') then
if(position=i) then
dis<="00000000";
end if;
end if;
if (i=2 or i=4) then
dis(0)<='1';
end if;
duan<=dis;
wei<=cat;
end process;
end a;

Answer 1

你的ENTITY的声明里面：
duan : out std_logic_vector(7 to 0);
wei : out std_logic_vector(5 to 0)

用downto。。
即改为
duan : out std_logic_vector(7 downto 0);
wei : out std_logic_vector(5 downto 0)
应该就行了，希望能帮到你

PS。要是看到了，麻烦采纳下啊。。。我很认真的答，但有一半以上的都没回应。。

Answer 2

需要帮你写吗