Question

一个关于VHDL的问题

library ieee;
use ieee.std_logic_1164.all;

entity ym is
port(a:in std_logic_vector(6 downto 0);
s:out std_logic_vector(2 downto 0);
b:out std_logic_vector(3 downto 0);
c:out std_logic_vector(2 downto 0));
end ;

process(a)
variable ss:std_logic_vector(2 downto 0);
variable bb:std_logic_vector(6 downto 0);
begin
ss(2):=a(6) xor a(5) xor a(4) xor a(2);
b(1)<=a(3) xor a(2) xor a(0);
b(0)<=a(3) xor a(1) xor a(0);
ss(1):=a(6) xor a(5) xor a(3) xor a(1);
ss(0):=a(6) xor a(4) xor a(3) xor a(0);
if ss> "000" then
case ss is
when "001" =>bb(0):= not bb(0);c<="000";
when "010" =>bb(1):= not bb(1);c<="001";
when "100" =>bb(2):= not bb(2);c<="010";
when "011" =>bb(3):= not bb(3);c<="011";
when "101" =>bb(4):= not bb(4);c<="100";
when "110" =>bb(5):= not bb(5);c<="101";
when "111" =>bb(6):= not bb(6);c<="110";
when others => null;c<="111";
end case;
else b<= a(6)&a(5)&a(4)&a(3);
end if;
s<=ss;
b<=bb(6)&bb(5)&bb(4)&bb(3);
end process;

end;
调试了就是有一个错误啊，有没有高手指点一下。

Answer 1

同学，首先，你少了一句：architecture XXXX of ym is 把这句加上；当然，后面还少了个begin
所以修改后的程序为：
===============================
library ieee;
use ieee.std_logic_1164.all;

entity ym is
port(a:in std_logic_vector(6 downto 0);
s:out std_logic_vector(2 downto 0);
b:out std_logic_vector(3 downto 0);
c:out std_logic_vector(2 downto 0));
end ;
architecture one of ym is
begin
process(a)
variable ss:std_logic_vector(2 downto 0);
variable bb:std_logic_vector(6 downto 0);
begin
ss(2):=a(6) xor a(5) xor a(4) xor a(2);
b(1)<=a(3) xor a(2) xor a(0);
b(0)<=a(3) xor a(1) xor a(0);
ss(1):=a(6) xor a(5) xor a(3) xor a(1);
ss(0):=a(6) xor a(4) xor a(3) xor a(0);
if ss> "000" then
case ss is
when "001" =>bb(0):= not bb(0);c<="000";
when "010" =>bb(1):= not bb(1);c<="001";
when "100" =>bb(2):= not bb(2);c<="010";
when "011" =>bb(3):= not bb(3);c<="011";
when "101" =>bb(4):= not bb(4);c<="100";
when "110" =>bb(5):= not bb(5);c<="101";
when "111" =>bb(6):= not bb(6);c<="110";
when others => null;c<="111";
end case;
else b<= a(6)&a(5)&a(4)&a(3);
end if;
s<=ss;
b<=bb(6)&bb(5)&bb(4)&bb(3);
end process;
end one;
=================
调试通过
=================
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Allocated 92 megabytes of memory during processing
Info: Processing ended: Thu Sep 25 14:27:42 2008
Info: Elapsed time: 00:00:00
Info: Quartus II Full Compilation was successful. 0 errors, 25 warnings

Answer 2

EAD