Question

EDA用VHDL语言写数字时钟

主要是24进制时部分怎么写
顺带整合部分有也可以

Answer 1

second:process (clks) is --秒
begin
if reset='1' then
Q1<="0000";Q0<="0000";
elsif clks'event and clks='1' then
if Q0 = "1001" then
Q0<="0000";
if Q1 = "0101" then
Q1<="0000";
else
Q1<=Q1+1;
end if;
else
Q0<=Q0+'1';
end if;
end if;
end process;
enmin<='1' when Q1="0000" and Q0="0000";

minute:process (enmin) is --分
begin
if reset='1' then
Q3<="0000";Q2<="0000";
elsif setmin='1' then
Q3<=a1;Q2<=a0;
elsif enmin'event and enmin='1' then
if Q2 = "1001" then
Q2<="0000";
if Q3 = "0101" then
Q3<="0000";
else
Q3<=Q3+1;
end if;
else
Q2<=Q2+'1';
end if;
end if;
end process;
enhour<='1' when Q3="0000" and Q2="0000";

alert<='1' when Q3="0000" and Q2="0000" and Q1="0000" and Q0="0000"; --整点报时

hour:process (enhour) is --时
begin
if reset='1' then
Q5<="0000";Q4<="0000";
elsif sethour='1' then
Q5<=a1;Q4<=a0;
elsif enhour'event and enhour='1' then
if Q5="0010" and Q4="0011" then
Q5<="0000";Q4<="0000";
else
if Q4="1001" then
Q4<="0000";Q5<=Q5+'1';
else
Q4<=Q4+'1';
end if;
end if;
end if;
end process;