Question

怎么在Xilinx的ISE里用Verilog写这一段

module sbox (
address,
clock,
q);
input [7:0] address;
input clock;
output [7:0] q;
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.address_b (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.data_a (),
.data_b (),
.q_b (),
.rden_b (),
.wren_a (),
.wren_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.width_a = 8,
altsyncram_component.widthad_a = 8,
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.init_file = "sbox.mif",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram";

endmodule

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Answer 1

这不就是verilog的吗。。除了最后那段儿。

Answer 2

楼主知道了吗？我也想问问T T