如何用verilog写8个流水灯
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module first_soft (clk, rst, led);//port
input clk, rst;
output [7:0] led;
reg [7:0] led;
reg [24:0] count;//计数器
reg [24:0] speed;//速度
reg [3:0] state;//状态,[3]=1:正转;[3]=0:翻转;{2,0}速度
always @(posedge clk or negedge rst)//自动变频流水灯
if (!rst)
begin
statelt;=4;d0;
ledlt;=8;b00000001;
countlt;=25;d0;
speedlt;=25;d20000000;
end
else
begin
countlt;=count+1;b1;
if (count==speed)
begin
countlt;=25;d0;//计数器复位
if (state[3]==0)//转移发光二极管
begin
ledlt;=ledlt;lt;1;b1;
if (led==8;b01000000) state[3]lt;=1;b1;
end
else
begin
ledlt;=led;;1;b1;
if (led==8;b00000010)
begin
case (state[2:0])
3;b000: begin speedlt;=25;d10000000; state[3:0]lt;=4;b0001; end
3;b001: begin speedlt;=25;d5000000; state[3:0]lt;=4;b0010; end
3;b010: begin speedlt;=25;d2500000; state[3:0]lt;=4;b0011; end
3;b011: begin speedlt;=25;d1200000; state[3:0]lt;=4;b0100; end
3;b100: begin speedlt;=25;d2500000; state[3:0]lt;=4;b0101; end
3;b101: begin speedlt;=25;d5000000; state[3:0]lt;=4;b0110; end
3;b110: begin speedlt;=25;d10000000; state[3:0]lt;=4;b0111; end
3;b111: begin speedlt;=25;d20000000; state[3:0]lt;=4;b0000; end
default: begin speedlt;=25;d20000000; state[3:0]lt;=4;b0000; end
endcase
end
end
end
end
endmodule
input clk, rst;
output [7:0] led;
reg [7:0] led;
reg [24:0] count;//计数器
reg [24:0] speed;//速度
reg [3:0] state;//状态,[3]=1:正转;[3]=0:翻转;{2,0}速度
always @(posedge clk or negedge rst)//自动变频流水灯
if (!rst)
begin
statelt;=4;d0;
ledlt;=8;b00000001;
countlt;=25;d0;
speedlt;=25;d20000000;
end
else
begin
countlt;=count+1;b1;
if (count==speed)
begin
countlt;=25;d0;//计数器复位
if (state[3]==0)//转移发光二极管
begin
ledlt;=ledlt;lt;1;b1;
if (led==8;b01000000) state[3]lt;=1;b1;
end
else
begin
ledlt;=led;;1;b1;
if (led==8;b00000010)
begin
case (state[2:0])
3;b000: begin speedlt;=25;d10000000; state[3:0]lt;=4;b0001; end
3;b001: begin speedlt;=25;d5000000; state[3:0]lt;=4;b0010; end
3;b010: begin speedlt;=25;d2500000; state[3:0]lt;=4;b0011; end
3;b011: begin speedlt;=25;d1200000; state[3:0]lt;=4;b0100; end
3;b100: begin speedlt;=25;d2500000; state[3:0]lt;=4;b0101; end
3;b101: begin speedlt;=25;d5000000; state[3:0]lt;=4;b0110; end
3;b110: begin speedlt;=25;d10000000; state[3:0]lt;=4;b0111; end
3;b111: begin speedlt;=25;d20000000; state[3:0]lt;=4;b0000; end
default: begin speedlt;=25;d20000000; state[3:0]lt;=4;b0000; end
endcase
end
end
end
end
endmodule
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