Question

VHDL跑马灯程序

我写了一个跑马灯的程序，可以选择四种模式，1从左到右亮2从右到左亮3两边向中间亮4中间向两边亮 写的程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity led is
port(clk : in std_logic;
rest : in std_logic;
input : in std_logic_vector(1 downto 0);
output: out std_logic_vector(7 downto 0)
);
end entity;

architecture one of led is --gezhong xinhao fuzhi
signal a1,fenpin: std_logic;
signal xinhao1 : std_logic_vector(7 downto 0);
signal xinhao2,xinhao3 : std_logic_vector(3 downto 0);
signal xinhao4,xinhao5: std_logic_vector(7 downto 0);
begin

p1:process(rest,fenpin,input) --if selector to select module
begin
if(rest='1') then
xinhao5<="00000000";
elsif (fenpin'event and fenpin='1') then
if input="00" then --module 1 left to right
xinhao1<=xinhao1+1;
a1<='1';
elsif input="01" then --module 2 right to left
xinhao1<=xinhao1-1;
a1<='1';
elsif input="10" then
xinhao2<=xinhao2+1;
xinhao3<=xinhao3+1;
xinhao4<=xinhao2&xinhao3;
a1<='0';
elsif input="11" then
xinhao2<=xinhao2-1;
xinhao3<=xinhao3-1;
xinhao4<=xinhao2&xinhao3;
a1<='0';
else
xinhao1<="00000000";
xinhao4<="00000000";
end if;
end if;
end process p1;

p2:process(clk)--fenpin qi
constant chanshu :integer:=2499;
variable x :integer;
begin
if (clk'event and clk='1') then
if x=2499 then
x:=0;
fenpin<= not fenpin;
else
x:=x+1;
end if;
end if;
end process p2;

p3:process(a1,fenpin)
begin
if (fenpin'event and fenpin='1') then
if a1='1'then
xinhao5<=xinhao1;
elsif a1='0' then
xinhao5<=xinhao4;
else
xinhao5<="00000000";
end if;
end if;
end process p3;
output<=xinhao5;

end architecture one;
但是编译的时候QUARTUS显示出错，显示如下
can't resolve multiple constant drivers for net"xinhao5[6]"
can't resolve multiple constant drivers for net"xinhao5[5]"
can't resolve multiple constant drivers for net"xinhao5[4]"
can't resolve multiple constant drivers for net"xinhao5[3]"
can't resolve multiple constant drivers for net"xinhao5[2]"
can't resolve multiple constant drivers for net"xinhao5[1]"
can't resolve multiple constant drivers for net"xinhao5[0]"
我是第一次编写数字系统，写的很糟糕，希望大家能帮我找找错，告诉我哪里错了。

Answer 1

这个问题是初学者肯定犯的错误，我刚学的时候也经常犯这个错误，这个问题是：xinhao5不能解决多个驱动,process语句是并行的，不能在多个process语句中同时对xinhao5赋值。你可以这样理解，process是并行的语句，它们有可能同时触发，假设多个包含对xinhao5赋值（一个以上）的process被触发了，那你说这时哪个process的赋值是有效的呢？所以，所以对xihao5的赋值只能出现在一个process里面

Answer 2

这是冲突，多个进程同时对一个变量进行赋值，假如1进程敏感列表是clk，让a=1了，又在2进程（敏感列表也有clk）中给a=2了，这就冲突了，不知道你能明白不。 有可能是直接冲突一目了然，有可能是间接地，在某处条件上冲突了，你再好好分析分析，有时间的话帮你看看

Answer 3

同意楼上的看法，虽然我用Verilog HDL，但也遇到过这种问题。原因就是，FPGA是并行的。你可能有地方同时对同一个变量做了修改。然后就会报错。
我用的是VerilogHDL ，不太懂VHDL，所以只能帮这么多了。呵呵