Question

如何利用vhdl语言对信号的高电平进行时间测量？

我知道是利用在高电平期间对clk进行计数，重点是如何进行编程，有没有大神指导，帮忙写一个程序，要准确的。在线等。

Answer 1

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY counter IS
GENERIC(n : positive := 16);
PORT(clk,en : IN std_logic;
counter_out : OUT std_logic_vector(n-1 DOWNTO 0));
END counter;
ARCHITECTURE behavioral OF counter IS
SIGNAL counter_t : std_logic_vector(n-1 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
IF en='1' THEN
counter_t <= counter_t + 1;
ELSE
counter_t <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(en)
BEGIN
IF falling_edge(en) THEN
counter_out <= counter_t;
END IF;
END PROCESS;
END behavioral;