每隔一段时间来一组方波 verilog语言实现
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module fangbo(
input rst,
input clk,
output reg wave)
reg [7:0] counter;
always(posedge clk)
begin
if(rst)
begin
count <= 0;
wave <= 0;
end
else if(count == 20)
begin
count <= 0;
wave <= 0;
end
else if(count <= 8)
begin
count <=count +1;
wave <= count[0];
end
else if(count < 20)
begin
count <=count +1;
wave <= 0;
end
end
endmodule
input rst,
input clk,
output reg wave)
reg [7:0] counter;
always(posedge clk)
begin
if(rst)
begin
count <= 0;
wave <= 0;
end
else if(count == 20)
begin
count <= 0;
wave <= 0;
end
else if(count <= 8)
begin
count <=count +1;
wave <= count[0];
end
else if(count < 20)
begin
count <=count +1;
wave <= 0;
end
end
endmodule
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