Question

高分求高人相助~一个Verilog程序编写的问题~

初学FPGA，想编写程序实现下面这个功能，但是无论如何一直都无法通过后仿真，走投无路只能求高人相助！
程序功能：测试人的反应时间
实现方法：基于A3P030芯片，4个按键，3个led灯，一个四位数码管。按键0提供复位信号；按键1与led1对应，作为测试开始控制；按键2和按键3与led2和led3对应，作为测试信号输入。测试开始时，先按下led1，延时5s后led1亮起，此时两名测试者以最快速度按下按键led2/led3，速度快者按键对应的led灯亮起，同时四位数码管显示出led1亮起到第一个按键按下的时间差，即两名测试者中反应时间短者的反应时间。

虽然程序很简单，但是总是存在很多的error，希望高手帮忙编写一个完整例程以供参考。请发至邮箱：molamola@126.com。
一旦录用必有重酬！多谢指教！

Answer 1

我把原理讲诉一下：
1.按键1是 按键2和按键3 的启动控制信号
2.按键2 与按键3 是互相矛盾的，只有一个会亮
分析，通过状态机实现，
当light2_ctrl ==1时进入light2状态
当light3_ctrl ==1时进入light3状态
然后请看我下面编写的程序

module delay_1s(
clock,
reset_n,
light1_ena,
light1_on

);

paramter MAX_VALUE = 6'd1000;

input clock;
input reset_n;

input light1_ena;//输入light1的启动信号
output light1_on;//经过1s后，给出light1亮灯信号

reg [5:0] counter;

always@(posedge clock or negedge reset_n)
begin
if(!reset_n)
counter <= 6'b0;
else if(counter<MAX_VALUE&&counter>6'd1)
counter <= counter + 1'b1;
else if(light1_ena)
counter <= 6'b1;
else
counter <=6'd0;
end

reg light1_on;
always@(posedge clock or negedge reset_n)
begin
if(!reset_n)
light1_on <= 1'b0;
else if(counter<=MAX_VALUE)
light1_on<= 1'b1;
end

endmodule
//------------------------------------

module light_ctrl(
clock,
reset_n,
light1_ctrl,
light2_ctrl,
light3_ctrl,

light2_ena,
light3_ena,
time_counter
);

input clock;
input reset_n;//low active

input light1_ctrl;//人按的按键
output light1_ena;//控制灯1亮灭的信号

input light2_ctrl;//人按的按键
output light2_ena;//控制灯1亮灭的信号

input light3_ctrl;//人按的
output light3_ena;//控制灯1亮灭的信号

output [3:0]time_counter; //接 4位的数码管的时间累计值,以clock为基

准的次数

//-----------------------
reg light2_ena;
reg light3_ena;

reg[2:0]curr_state;
reg[2:0]next_state;
reg [3:0]time_counter；

parameter IDLE = 3'b0;
parameter LIGHT1 = 3'b100;
parameter LIGHT2 = 3'b101;
parameter LIGHT3 = 3'b110;
parameter LIGHT_ALL = 3'b111;
//
always@(posedge clock or negedge reset_n)
begin
if(!reset_n)
curr_state <= IDLE;
else
curr_state <= next_state;
end

always@(*)
begin
next_state = curr_state;
case(curr_state)
IDLE:
if(light1_ctrl)
next_state = LIGHT1;
else
next_state = IDLE;
LIGHT1:
begin
case({light3_ctrl,light2_ctrl})
2'b00: next_state= LIGHT1;
2'b10: next_state= LIGHT3;
2'b01: next_state= LIGHT2;

default: next_state= LIGHT_ALL;//LIGHT_ALL

state
endcase
end//LIGHT1
LIGHT2:
begin

next_state= LIGHT2;
end
LIGHT3:
begin
next_state= LIGHT3;
end

LIGHT_ALL:
begin
next_state= LIGHT_ALL;
end
default: next_state = IDLE;
endcase

end

always@(posedge clock or negedge reset_n)
begin
if(!reset_n)
light2_ena <= 1'b0;
else
light2_ena <= (curr_state==LIGHT2)|(curr_state==LIGHT_ALL);
end

always@(posedge clock or negedge reset_n)
begin
if(!reset_n)
light3_ena <= 1'b0;
else
light3_ena <= (curr_state==LIGHT3)|(curr_state==LIGHT_ALL);
end

always@(posedge clock or negedge reset_n)
begin
if(!reset_n)
time_counter <= 4'b0;
else if(curr_state==LIGHT1)
time_counter <= time_counter + 1'b1;
end
endmodule

//------------------------------------

module light_ctrl_top(
clock,
reset_n,
light1_ctrl,
light2_ctrl,
light3_ctrl,

light1_on,
light2_on,
light3_on,
time_counter

);

input clock;
input reset_n;

input light1_ctrl;
input light2_ctrl;
input light3_ctrl;

output light1_on;
output light2_on;
output light3_on;

output[3:0] time_counter;
//---------------------------
delay_1s u_delay_1s(
.clock(clock),
.reset_n(reset_n),
.light1_ena(light1_ctrl),
.light1_on(light1_on)

);

//-----------------------------
light_ctrl u_light_ctrl(
.clock(clock),
.reset_n(reset_n),
.light1_ctrl( light1_on ),
.light2_ctrl( light2_ctrl ),
.light3_ctrl( light3_ctrl ),
.light2_ena(light2_on ),
.light3_ena(light2_on ),
.time_counter( time_counter)
);

endmodule

Answer 2

很简单