Question

VHDL语言问题？

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xulie is
port( clk:in std_logic;
dout:out std_logic
);
end;
architecture one of xulie is
signal reg:std_logic_vector(7 downto 0);
begin
reg<="10110101";
dout<=reg(7);
process(clk)
begin

if clk'event and clk='1' then
reg<=reg(6 downto 0) & reg(7);
end if;

end process;
end;
编写的一个序列发生器，请问我错在哪了？谢谢！

Answer 1

reg<="10110101";
应该在定义时赋初值
你那样写会和进程里面的操作冲突，已经编译通过
程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xulie is
port( clk:in std_logic;
dout:out std_logic
);
end;
architecture one of xulie is
signal reg:std_logic_vector(7 downto 0):="10110101";
begin
dout<=reg(7);
process(clk)
begin

if clk'event and clk='1' then
reg<=reg(6 downto 0) & reg(7);
end if;

end process;
end;