Question

求助：用Verilog例化ROM出错

用MEGAWizard生成了一个ROM模块，但编译时出错
顶层文件：
module ram_test(clkin,out);
input clkin;
output[7:0] out;
reg[7:0] add;
always @(posedge clkin)
begin
if(add==255)
add=0;
rom1 m0(.address (add),.q (out));
add=add+1;
end
endmodule

ROM模块封装文件：
module rom1 (
address,
q);

input [7:0] address;
output [7:0] q;

wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];

lpm_rom lpm_rom_component (
.address (address),
.q (sub_wire0),
.memenab (1'b1),
.inclock (1'b1),
.outclock (1'b1));
defparam
lpm_rom_component.intended_device_family = "FLEX10K",
lpm_rom_component.lpm_address_control = "UNREGISTERED",
lpm_rom_component.lpm_file = "initual.mif",
lpm_rom_component.lpm_outdata = "UNREGISTERED",
lpm_rom_component.lpm_type = "LPM_ROM",
lpm_rom_component.lpm_width = 8,
lpm_rom_component.lpm_widthad = 8;

endmodule

错误信息：
Error (10170): Verilog HDL syntax error at ram_test.v(9) near text "m0"; expecting "<=", or "="

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Answer 1

怎么能在always中例化模块呢