Question

vhdl语言将1mhz的时钟频率分为400分频和800分频

系统时钟为1MHZ求VHDL语言编写的程序输出为400分频和800分频
请高手帮帮忙~

Answer 1

我帮你写了个，已经通过波形仿真。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fp is
port( clk :in std_logic;--1MHz时钟输入
clk1,clk2 :buffer std_logic;--clk1为400分频，clk2为800分频
reset :in std_logic
);
end fp;
architecture fps of fp is
begin
process(clk,reset)
variable count1:integer range 400 downto 0;
variable count2:integer range 800 downto 0;
begin
if reset='1' then
count1:=0;
count2:=0;
clk1<='0';
clk2<='0';
elsif rising_edge(clk) then
count1:=count1+1;
count2:=count2+1;
if count1=400 then
clk1<=not clk1;
count1:=0;
end if;
if count2=800 then
count2:=0;
clk2<=not clk2;
end if;
end if;
end process;
end fps;

Answer 2

400=(2^40*25
800=(2^5)*25

做个25分频即可,最简单的方法就是counter到25就reset