Question

VHDL多模块port map（）问题。

我用Xilinx写了三个VHDL文件，pocfile，printfile,top。top用于链接pocfile和printfile。
我在top里面这样写的：
头文件不写了
entity top is port
(
---processor与poc的接口
IRQ: out std_logic;
CLK: in std_logic;
RW: in std_logic;
Data:inout std_logic_vector(7 downto 0);
A: in std_logic_vector(2 downto 0);
CS: in std_logic
);
end top;

architecture Behavioral of top is

component pocfile
port
(
---processor与poc的接口
IRQ:out std_logic;
CLK: in std_logic;
RW: in std_logic;
Data:buffer std_logic_vector(7 downto 0);
A: in std_logic_vector(2 downto 0);
CS: in std_logic;
---poc寄存器
SR: inout std_logic_vector(7 downto 0);
BR: inout std_logic_vector(7 downto 0);
---与printer的接口
RDY: IN STD_LOGIC;
TR: out std_logic;
PD: OUT std_logic_vector(7 downto 0)
);
end component;
component prinfile is
port
(
CLK: in std_logic;
RDY: out std_logic;
TR: in std_logic;
PD: IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;

---下面是配置
for poc_exp:pocfile
use entity work.pocfile(Behavioral);
for pri_exp:printfile
use entity work.printfile(Behavioral);
---配置结束
signal s1:std_logic;
signal s2:std_logic;
signal s3:std_logic_vector(7 downto 0);
signal s4:std_logic;
begin
poc_exp: component pocfile port map(S1<=PD,S2<=TR,S3<=RDY,S4<=CLK);
pri_exp: component printfile port map(S1<=PD,S2<=TR,S3<=RDY,S4<=CLK);
end Behavioral;
结果爆出错误：（其中两处）
ERROR:HDLCompiler:69 - "F:\VHDL\poc\mypoc\top.vhd" Line 78: <printfile> is not declared.
ERROR:HDLCompiler:69 - "F:\VHDL\poc\mypoc\top.vhd" Line 87: <pd> is not declared.

Answer 1

没有细看。打眼一看，发现元件例化语句的端口映射表内关联符"=>"写成了赋值符号"<="，这在语法上就不正确了。