Question

(FPGA)Xilinx的Nexys2开发板时钟管脚分配问题(verilog)

一个小程序, 分配管脚前编译通过, 分配后报错, 求修改方案
错误提示为:
ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component <cp_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y10>. The IO component <cp> is
placed at site <IPAD59>. This will not allow the use of the fast path between the IO and the Clock buffer. If this
sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf
file to demote this message to a WARNING and allow your design to continue. However, the use of this override is
highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be
corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock rule.
< NET "cp" CLOCK_DEDICATED_ROUTE = FALSE; >
其中, 我的管脚分配是这样的:

NET "cp" LOC = B18;
NET "din" LOC = G18;
NET "dout[0]" LOC = J14;
NET "dout[1]" LOC = J15;
NET "dout[2]" LOC = K15;
NET "dout[3]" LOC = K14;
NET "dout[4]" LOC = E17;
NET "dout[5]" LOC = P15;
NET "dout[6]" LOC = F4;
NET "dout[7]" LOC = R4;
NET "rst" LOC = H13;

附源代码:
module ShitReg(
input cp,
input rst,
input din,
output reg [7:0] dout
);

always @(posedge cp)
begin
dout = dout << 1;
dout[0] = din;
end
endmodule

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Answer 1

NET "cp" LOC = B18;
NET "din" LOC = G18;
NET "dout[0]" LOC = J14;
NET "dout[1]" LOC = J15;
NET "dout[2]" LOC = K15;
NET "dout[3]" LOC = K14;
NET "dout[4]" LOC = E17;
NET "dout[5]" LOC = P15;
NET "dout[6]" LOC = F4;
NET "dout[7]" LOC = R4;
NET "rst" LOC = H13;
< NET "cp" CLOCK_DEDICATED_ROUTE = FALSE; >

修改成这个样子就好了，这是时序约束造成的。

追问

谢谢'！