Question

急！vhdl编写fpga程序！10小时内需要！

用ise编写程序，实现功能，芯片为 xilinx 的， 实现，按平板上的按钮一下则数码管相对应的那个显示数字加1。再按一下，再加1，当到9时再按一下就成为0，重新按下继续计数。

只用其中一个按钮和一个数码管即可。
最好写简单注释。

很急！10小时内需要！

谢谢！！

Answer 1

(1)先做一个消抖，存到文件debounce.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity debounce is
generic (
CLK_FREQ_MHz : integer := 20; --in MHz
BUTTON_PRESS_STATUS : std_logic := '0'
);
port (
reset_n : in std_logic;
clk : in std_logic;
btnIn : in std_logic;
btnPressed : out std_logic
);
end debounce;

architecture debounce_arch of debounce is

constant MAX_MS_CNT : integer := CLK_FREQ_MHz * 1000 - 1;
signal msCnt : integer range 0 to MAX_MS_CNT;
signal msClk : std_logic; --做一个毫秒脉冲，每1毫秒对按钮采样一次
signal btnIn_q : std_logic_vector(9 downto 0); --记住最后10次采样
signal btn : std_logic;
signal btn_q : std_logic;

begin
--产生毫秒脉冲
process(reset_n, clk)
begin
if reset_n = '0' then
msCnt <= 0;
msClk <= '0';
elsif rising_edge(clk) then
if msCnt >= MAX_MS_CNT then
msCnt <= 0;
msClk <= '1';
else
msCnt <= msCnt + 1;
msClk <= '0';
end if;
end if;
end process;

--记住最后10次采样
process(reset_n, clk)
begin
if reset_n = '0' then
btnIn_q <= (others => not BUTTON_PRESS_STATUS);
elsif rising_edge(clk) then
if msClk = '1' then
btnIn_q <= btnIn_q(btnIn_q'left-1 downto 0) & btnIn;
else
btnIn_q <= btnIn_q;
end if;
end if;
end process;

process(reset_n, clk)
variable all_samples_are_pressed : std_logic_vector(btnIn_q'left downto 0) := (others => BUTTON_PRESS_STATUS);
begin
if reset_n = '0' then
btn <= '0';
btn_q <= '0';
elsif rising_edge(clk) then
if btnIn_q = all_samples_are_pressed then
btn <= '1'; --最后10次采样都是按下状态，就确认按钮按下（10ms消抖）
elsif btnIn_q = not all_samples_are_pressed then
btn <= '0'; --最后10次采样都是抬起状态，就确认按钮抬起（10ms消抖）
else
btn <= btn; --否则保持不变
end if;
btn_q <= btn;
end if;
end process;

btnPressed <= '1' when btn = '1' and btn_q = '0' else '0'; --按钮按下上升沿检测

end debounce_arch;

(2)做一个加法器，存到文件adder.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity adder is
port (
reset_n : in std_logic;
clk : in std_logic;
adderEn : in std_logic;
data : out std_logic_vector(3 downto 0);
dataValid : out std_logic
);
end adder;

architecture adder_arch of adder is

signal cnt : std_logic_vector(3 downto 0);

begin

process(reset_n, clk)
begin
if reset_n = '0' then
cnt <= x"0";
dataValid <= '0';
elsif rising_edge(clk) then
if adderEn = '1' then --将被替换成，按钮按下时，计数+1
if cnt >= x"9" then
cnt <= x"0";
else
cnt <= cnt + 1;
end if;
dataValid <= '1';
else
cnt <= cnt;
dataValid <= '0';
end if;
end if;
end process;

data <= cnt;

end adder_arch;

(3)做7段数码管显示，存到文件SevenSegment.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity SevenSegment is
generic (
LED_ON : std_logic := '0'
);
port (
reset_n : in std_logic;
clk : in std_logic;
data : in std_logic_vector(3 downto 0);
dataValid : in std_logic;
ledOut : out std_logic_vector(6 downto 0)
);
end SevenSegment;

architecture SevenSegment_arch of SevenSegment is

constant LED_OFF : std_logic := not LED_ON;
signal led : std_logic_vector(6 downto 0);

begin

-- --a--
-- |f |b
-- --g--
-- |e |c
-- --d--

process(reset_n, clk)
begin
if reset_n = '0' then
led <= LED_ON & LED_ON & LED_ON & LED_ON & LED_ON & LED_ON &LED_OFF; --display 0
elsif rising_edge(clk) then
if dataValid = '1' then
case data is --a b c d e f g
when x"0" =>
led <= LED_ON & LED_ON & LED_ON & LED_ON & LED_ON & LED_ON & LED_OFF; --display 0
when x"1" =>
led <= LED_OFF & LED_ON & LED_ON & LED_OFF & LED_OFF & LED_OFF & LED_OFF; --display 1
when x"2" =>
led <= LED_ON & LED_ON & LED_OFF & LED_ON & LED_ON & LED_OFF & LED_ON ; --display 2
when x"3" =>
led <= LED_ON & LED_ON & LED_ON & LED_ON & LED_OFF & LED_OFF & LED_ON ; --display 3
when x"4" =>
led <= LED_OFF & LED_ON & LED_ON & LED_OFF & LED_OFF & LED_ON & LED_ON ; --display 4
when x"5" =>
led <= LED_ON & LED_OFF & LED_ON & LED_ON & LED_OFF & LED_ON & LED_ON ; --display 5
when x"6" =>
led <= LED_ON & LED_OFF & LED_ON & LED_ON & LED_ON & LED_ON & LED_ON ; --display 6
when x"7" =>
led <= LED_ON & LED_ON & LED_ON & LED_OFF & LED_OFF & LED_OFF & LED_OFF; --display 7
when x"8" =>
led <= LED_ON & LED_ON & LED_ON & LED_ON & LED_ON & LED_ON & LED_ON ; --display 8
when x"9" =>
led <= LED_ON & LED_ON & LED_ON & LED_ON & LED_OFF & LED_ON & LED_ON ; --display 9
when others =>
led <= (others => LED_OFF);
end case;
else
led <= led;
end if;
end if;
end process;

ledOut <= led;

end SevenSegment_arch;

(4)最后，综合到一起，存到文件top.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity top is
generic (
CLK_FREQ_MHz : integer := 20; --可以修改成你的系统时钟频率，以MHz为单位
BUTTON_PRESS_STATUS : std_logic := '0'; --指定按钮按下时，是逻辑0还是1
LED_ON : std_logic := '0' --指定数码管点亮需要输出0还是1
);
port (
reset_n : in std_logic;
clk : in std_logic;
btnIn : in std_logic;
ledOut : out std_logic_vector(6 downto 0)
);
end top;

architecture top_arch of top is

component debounce
generic (
CLK_FREQ_MHz : integer := 20; --in MHz
BUTTON_PRESS_STATUS : std_logic := '0'
);
port (
reset_n : in std_logic;
clk : in std_logic;
btnIn : in std_logic;
btnPressed : out std_logic
);
end component;

component adder
port (
reset_n : in std_logic;
clk : in std_logic;
adderEn : in std_logic;
data : out std_logic_vector(3 downto 0);
dataValid : out std_logic
);
end component;

component SevenSegment
generic (
LED_ON : std_logic := '0'
);
port (
reset_n : in std_logic;
clk : in std_logic;
data : in std_logic_vector(3 downto 0);
dataValid : in std_logic;
ledOut : out std_logic_vector(6 downto 0)
);
end component;

signal btnPressed : std_logic;
signal data : std_logic_vector(3 downto 0);
signal dataValid : std_logic;

begin

debounce_inst : debounce
generic map (
CLK_FREQ_MHz => CLK_FREQ_MHz, --in MHz
BUTTON_PRESS_STATUS => BUTTON_PRESS_STATUS
)
port map(
reset_n => reset_n,
clk => clk,
btnIn => btnIn,
btnPressed => btnPressed
);

addr_inst : adder
port map (
reset_n => reset_n,
clk => clk,
adderEn => btnPressed,
data => data,
dataValid => dataValid
);

SevenSegment_inst : SevenSegment
generic map (
LED_ON => LED_ON
)
port map (
reset_n => reset_n,
clk => clk,
data => data,
dataValid => dataValid,
ledOut => ledOut
);

end top_arch;

(5)你只要修改top.vhd里generic的定义，设定时钟频率、按钮按下状态和数码管点亮状态即可

Answer 2

你说的实现功能就是数字频率计中的十进制计数器模块。
给一个CLK时钟信号，CKL=‘1’时，预置门信号控制端每给一个上升沿触发计数器开始计数。具体使用VHDL语言编写：
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl2 is /定义实体名vhdl2/
port(clk,reset,en: in std_logic;
qa,qb,qc,qd: out std_logic);
end vhdl2; /以上都是实体定义部分/
architecture behave of vhdl2 is
signal count_4: std_logic_vector(3 downto 0);
begin
qa<=count_4(0);
qb<=count_4(1);
qc<=count_4(2);
qd<=count_4(3); /定义4个输出端/
process(clk,reset)
begin
if (reset='0') then
count_4<="0000";
elsif(clk'event and clk='1') then
if(en='1') then
if(count_4="1001") then /二进制表示即4个输出端输出为9/
count_4<="0000"; /二进制表示即4个输出端输出为0/
else
count_4<=count_4+'1'; /加法计数，每次加1/
end if;
end if;
end if;
end process;
end behave; /以上是结构体部分/
PROCESS以后是进程部分。
其中CLK是时钟信号端，RESET是复位端，负责信号清零，qa到qd是四个输出，输出四位二进制，通过译码显示出对应的十进制数。以上是加法十进制计数器，如果需要减法，我再给你。所谓的按钮其实就是CLK控制端，通过预置闸门信号控制的原理，将CLK换下即可。以上程序运用MAXPLUSII或者QUARTUSII都可仿真实现。
希望对你有所帮助。