Question

求助一段用Verilog 写 testbench

module lamp_test;

// Inputs
reg clk;
reg S1;
reg S2;
reg S3;

// Outputs
wire F;

// Instantiate the Unit Under Test (UUT)
lamp_controller uut (
.clk(clk),
.S1(S1),
.S2(S2),
.S3(S3),
.F(F)
);

initial begin
// Initialize Inputs
clk = 0;
S1 = 0;
S2 = 0;
S3 = 0;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

end
我刚学这个啦，是一个模拟楼道灯声控开关的程序。可是我不会写那个仿真文件，系统直接生成了这一段。下面是电路的源代码。有木有大神帮忙弄弄，万分感谢！。（仿真的要求是让S1先打开，然后等灯熄灭之后再打开S2，然后灯灭，S3打开，clk是时钟）
module lamp_controller(clk, S1, S2, S3, F);
parameter COUNTER = 8;
input clk, S1, S2, S3;
output F;
wire w;
regy;
reg[COUNTER-1 : 0] count;
initial count <= 0;
assign w = S1^ S2 ^ S3;

always @ (posedgeclk)
if (w || count < 8‘hFF) begin
y <= 1;
count<= count + 1;
end else begin
y <= 0;
count<= count;
end
assignF = y;
endmodule

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Answer 1

`timescale 1ns/1ps  

 

module lamp_test;

// Inputs
reg clk;
reg S1;
reg S2;
reg S3;

// Outputs
wire F;

// Instantiate the Unit Under Test (UUT)
lamp_controller uut (
.clk(clk),
.S1(S1),
.S2(S2),
.S3(S3),
.F(F)
);

initial begin
// Initialize Inputs
clk = 0;
S1 = 0;
S2 = 0;
S3 = 0;

// Wait 100 ns for global reset to finish
#100;

 // Add stimulus here

#100    S1 = 1'b1;

@(negedge F)

#100    S2 = 1'b1;

@(negedge F)

#100    S3 = 1'b1;

#10000    $stop;

 end

//产生时钟激励

initial begin

forever    #10    clk = ~clk;

end  

 endmodule

Answer 2

//add simulus here
reg [1:0] state=2'b0;
s1=1;
always@(posedge clk)
begin
case (state)

2'b0: begin if(~F) begin state<=2'b1; s2<=1'b1; end end

2'b1: begin s1<=0; if(~F) begin state <= 2'b2; s3<=1'b1; end end

2'b2: state<=2'b0;

default: begin s1<=1'b0;s2<=1'b0;s3<=1'b0; state<=2'b0; end
endcase
end