Question

急求！vhdl语言中一个进程只能有一个上升沿判别语句下面的程序要怎么改，或者用verilog写是不是就可以了

程序很短，32位并转串，麻烦各位大神看看！
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY zhuanhuan IS
PORT
( clk_rck : in std_logic;
clk_sck : in std_logic;
Q : in STD_LOGIC_VECTOR(31 DOWNTO 0);
dout: out STD_LOGIC

);
END zhuanhuan;
ARCHITECTURE BRENDA OF zhuanhuan IS
SIGNAL i : integer range 0 to 31;
signal count:STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
process (clk_rck)
begin
if clk_rck'event and clk_rck='1' then
count<=Q;
for t in 100 downto 0 loop
if clk_sck'event and clk_sck='1' then
dout<=Q(i);
i<=i+1;
end if;
end loop;
end if;
end process;
end BRENDA;

Answer 1

你在process的敏感列表里加上另一个时钟，然后里面照着另一个时钟写，有问题吗？我用verilog的vhdl也不是特别熟悉。