Question

会VHDL语言的帮帮我吧！看看下面程序有问题没，帮我运行一下。谢谢啦……

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY moore IS
PORT（ clk, data：IN STD_LOGIC;
zo :OUT STD_LOGIC);
END moore;

ARCHITECTURE a OF moore IS
TYPE STATE IS (S1,S2,S3,S4,S5,S6,S7,S8);
SIGNAL pstate :STATE;
BEGIN
PROCESS(clk)
BEGIN
IF (clk’EVENT AND clk=‘1’) THEN
CASE pstate is
WHEN S1=> IF data=‘1’ THEN pstate<=S2; ELSE pstate<=S1;
END IF;
WHEN S2=> IF data=‘1’ THEN pstate<=S3; ELSE pstate<=S1;
END IF;
WHEN S3=> IF data=‘1’ THEN pstate<=S4; ELSE pstate<=S1;
END IF;
WHEN S4=> IF data=‘0’ THEN pstate<=S5; ELSE pstate<=S4;
END IF;
WHEN S5=> IF data=‘0’ THEN pstate<=S6; ELSE pstate<=S2;
END IF;
WHEN S6=> IF data=‘1’ THEN pstate<=S7; ELSE pstate<=S1;
END IF;
WHEN S7=> IF data=‘0’ THEN pstate<=S8; ELSE pstate<=S3;
END IF;
WHEN S8=> IF data=‘1’ THEN pstate<=S2; ELSE pstate<=S1;
END IF;
END CASE;
END IF;
END PROCESS;
zo<=‘1’ WHEN pstate=s8 ELSE ‘0’;
END a;

Answer 1

没什么大问题，就是有的地方没有在英文状态下输入，下面的是已经改好的，基液并搏衡物且编译通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY moore IS
PORT (clk,data: IN STD_LOGIC;
zo :OUT STD_LOGIC);
END moore;

ARCHITECTURE a OF moore IS
TYPE STATE IS (S1,S2,S3,S4,S5,S6,S7,S8);
SIGNAL pstate :STATE;
BEGIN
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
CASE pstate is
WHEN S1=> IF data='1' THEN pstate<=S2; ELSE pstate<=S1;
END IF;
WHEN S2=> IF data='1' THEN pstate<=S3; ELSE pstate<=S1;
END IF;
WHEN S3=> IF data='1' THEN pstate<=S4; ELSE pstate<=S1;
END IF;
WHEN S4=> IF data='0' THEN pstate<=S5; ELSE pstate<=S4;
END IF;
WHEN S5=> IF data='0' THEN pstate<=S6; ELSE pstate<=S2;
END IF;
WHEN S6=> IF data='1' THEN pstate<=S7; ELSE pstate<=S1;
END IF;
WHEN S7=> IF data='0' THEN pstate<=S8; ELSE pstate<=S3;
END IF;
WHEN S8=> IF data='1' THEN pstate<拦侍=S2; ELSE pstate<=S1;
END IF;
END CASE;
END IF;
END PROCESS;
zo<='1' WHEN pstate=s8 ELSE '0';
END a;

Answer 2

运行了，楼上说的对薯含，把分给上面吧，把单引号和开头一个括号换成英文的就行了，还有你的运行环境是什么，我用的是quartus 8.0，如果编译环境不一样可能结果会有猛手核不同枝掘

Answer 3

3个警告!无所谓啦,小场面!

Answer 4

帮你运行了，没有错误也没有警告！！！！