Question

DC综合时出现这种违列该怎么解决

Answer 1

在滑桥顶层文件中,我的时钟(sclk)复位(rst)信号设置为:set_dont_touch_network.但dc综合显
示有亏让斗违列,该怎么去解销磨决?
Information: Updating design information... (UID-85)
Warning: set_dont_touch_network is used for clock 'ANALOG/fs_clk', for which no sources are specified. (UID-997)
Warning: Design 'maxxtop' contains 2 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)

****************************************
Report : constraint
-all_violators
Design : maxxtop
Version: 2002.05
Date : Thu May 20 10:44:50 2004
****************************************

max_transition
Required Actual
Net Transition Transition Slack
-----------------------------------------------------------------
rst (dont_touch) 2.90 6027.06 -6024.16 (VIOLATED)
MAXX/FSC/N37 (dont_touch)
2.90 486.76 -483.86 (VIOLATED)

max_fanout
Required Actual
Net Fanout Fanout Slack
-----------------------------------------------------------------
rst (dont_touch) 7.40 1117.77 -1110.37 (VIOLATED)

max_capacitance
Required Actual
Net Capacitance Capacitance Slack
-----------------------------------------------------------------
rst (dont_touch) 0.15 1002.06 -1001.91 (VIOLATED)

max_area
Required Actual
Design Area Area Slack
-----------------------------------------------------------------
maxxtop 0.00 19381.99 -19381.99 (VIOLATED)