Question

MAX+PLUS II 编程出错 求大神解答！！

这是由宏模块LPM_FIFO自动生成的程序 但是编译的时候缺有好多ERROR 相当不明白
源程序：
LIBRARY IEEE;
USE IEEE._STD_LOGIC_1164.ALL;
ENTITY FIFO2 IS
PORT(DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WRREQ:IN STD_LOGIC;
RDREQ:IN STD_LOGIC;
CLOCK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
FULL:OUT STD_LOGIC);
END FIFO2;
ARCHITECTURE SYN OF FIFO2 IS
SIGNAL SUB_WIRE0:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SUB_WIRE1:STD_LOGIC;
COMPONENT LPM_FIFO
GENERIC (LPM_WIDTH:NATURAL;
LPM_NUMWORDS:NATURAL;
LPM_WIDTHU:NATURAL;
LPM_SHOWAHEAD:STRING;
LPM_HINT:STRING);
PORT(RDREQ:IN STD_LOGIC;
CLOCK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
WRREQ:IN STD_LOGIC;
DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FULL:OUT STD_LOGIC);
END COMPONENT;
BEGIN
Q<=SUB_WIRE0(7 DOWNTO 0);FULL<=SUB_WIRE1;
IPM_FIFO_COMPONENT:IPM_FIFO
GENERIC MAP(LPM_WIDTH=>8,
LPM_NUMWORDS=>512,
LPM_WIDTHU=>9,
LPM_SHOWAHEAD=>"OFF",
LPM_HINT=>"USE_EAB=ON,MAXIMIZE_SPEED=5")
PORT MAP(RDREQ=>RDREQ,CLOCK=>CLOCK,WRREQ=>WRREQ,DATA=>DATA,Q=>SUB_WIRE0,FULL=>SUB_WIRE1);
END SYN;
以下是错误信息：
Info：Selecting a device from 'MAX7000S'family for AUTO device 'fifo2'
Warning:Network license not available for the "Multichip Partitioner"feature
Error:Project does not fit in specified device(s)
Error:No fit found,generating Report File
Error:Project requires too many (4715/256)logic cells
Error:Project requires too many(3880/256)shareable expanders
Info:No fit possible with the current device
Info:Chip 'fifo2'did not fit into AUTO device ‘EPM7256SRC208-7’

Answer 1

你在assign->device选择一个芯片试试看！！！