Question

设计分频器的VHDL实现 时钟输入频率为50Mhz，带低电平复位reset，时钟输出频率为1Mhz

请问代码怎么写，谢谢！

Answer 1

library ieee;
use ieee.std_logic_1164.all;
entity div is
generic(n:integer :=50);
port (clk,reset_n:in std_logic;
q:out std_logic);
end div;
architecture behave of div is
signal count :integer range n-1 downto 0:=n-1;
begin
process(clk,reset_n)
begin
if reset_n='0' then
count <= n-1;
elsif rising_edge(clk) then
count<=count-1;
if count>=n/2 then
q<='0';
else
q<='1';
end if;
if count<=0 then
count<=n-1;
end if;
end if;
end process;
end behave;