Question

急求中文解释VHDL源程序！！要详细解释

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY speed IS
PORT(
clk :IN STD_LOGIC;
reset:IN STD_LOGIC;
start:IN STD_LOGIC;
stop :IN STD_LOGIC;
sp :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
clkout:OUT STD_LOGIC
);
END speed;

ARCHITECTURE rtl OF speed IS
BEGIN
PROCESS(clk,reset,stop,start,sp)
TYPE state_type IS(s0,s1);
VARIABLE s_state:state_type;
VARIABLE cnt:integer RANGE 0 TO 28;
VARIABLE kinside:INTEGER RANGE 0 TO 30;
BEGIN
CASE sp IS
WHEN "000"=>kinside:=0;
WHEN "001"=>kinside:=28;
WHEN "010"=>kinside:=24;
WHEN "011"=>kinside:=20;
WHEN "100"=>kinside:=16;
WHEN "101"=>kinside:=12;
WHEN "110"=>kinside:=8;
WHEN "111"=>kinside:=4;
END CASE;

IF reset='1'THEN
s_state:=s0;

ELSIF clk'EVENT AND clk='1'THEN
CASE s_state IS
WHEN s0=>
cnt:=0;
clkout<='0';
IF start='1'THEN
s_state:=s1;
ELSE
s_state:=s0;
END IF;

WHEN s1=>
clkout<='0';
IF stop='1'THEN
s_state:=s0;
ELSIF sp="000"then
s_state:=s1;
ELSIF cnt=kinside THEN
cnt:=0;
clkout<='1';
s_state:=s1;
ELSE
cnt:=cnt+1;
s_state:=s1;
END IF;
END CASE;
END IF;
END PROCESS;
END rtl;

希望大家能帮帮忙。。急用！！

Answer 1

流程图给上了，这是用状态机来写的程序，单纯用中文解释是说不太清的，反而用流程图一目了然些，这应该是一个控制程序，结合一楼的答案，就可以了。

Answer 2

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY speed IS
PORT(
clk :IN STD_LOGIC; 定义输入
reset:IN STD_LOGIC;
start:IN STD_LOGIC;
stop :IN STD_LOGIC;
sp :IN STD_LOGIC_VECTOR(2 DOWNTO 0); 定义输入数组
clkout:OUT STD_LOGIC 定义输出
);
END speed;

ARCHITECTURE rtl OF speed IS
BEGIN
PROCESS(clk,reset,stop,start,sp) 定义敏感信号，（）里边的任何一个信号变化，则程序执行
TYPE state_type IS(s0,s1);
VARIABLE s_state:state_type; 定义变量，只能在进程里边用
VARIABLE cnt:integer RANGE 0 TO 28;
VARIABLE kinside:INTEGER RANGE 0 TO 30;
BEGIN 开始逻辑运行
CASE sp IS
WHEN "000"=>kinside:=0; case语句，当sp是“000”的时候， kinside赋值为0
WHEN "001"=>kinside:=28;
WHEN "010"=>kinside:=24;
WHEN "011"=>kinside:=20;
WHEN "100"=>kinside:=16;
WHEN "101"=>kinside:=12;
WHEN "110"=>kinside:=8;
WHEN "111"=>kinside:=4;
END CASE;

IF reset='1'THEN
s_state:=s0;

ELSIF clk'EVENT AND clk='1'THEN 如果clk开个上升沿
CASE s_state IS
WHEN s0=>
cnt:=0;
clkout<='0';
IF start='1'THEN
s_state:=s1;
ELSE
s_state:=s0;
END IF;

WHEN s1=>
clkout<='0';
IF stop='1'THEN
s_state:=s0;
ELSIF sp="000"then
s_state:=s1;
ELSIF cnt=kinside THEN
cnt:=0;
clkout<='1';
s_state:=s1;
ELSE
cnt:=cnt+1;
s_state:=s1;
END IF;
END CASE;
END IF;
END PROCESS;
END rtl;