Question

用VHDL语言描述一个分频器，将1000HZ分频成1HZ,

用VHDL语句描述一个分频器。将1000HZ变成1HZ.最好是基于74LS90的。

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ffpin is
port (clk1k:in std_logic;
ft:out std_logic);
end ffpin;
architecture a of ffpin is
signal fm:std_logic;
begin
process(clk1k)
variable num:integer range 0 to 1000;
begin

if clk1k'event and clk1k='1' then
if num<500 then
num:=num+1;
else
num:=1;
fm<=not fm;
end if ;
end if;
ft<=fm;
end process;
end a;

这个程序输入为1kHz时，输出为1Hz

Answer 2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned;
entity share is
generic (n:integer:=1000);
port(clk:in std_logic;
cout:out std_logic);
end share;
architecture rtl of share is
signal counter:integer:=0;
begin
process(clk)
begin
if(clk'event and clk='1') then
if((n rem 2)=0)then
if(counter<n/2) then
cout<='0';
counter<=counter+1;
elsif(counter<n-1) then
cout<='1';
counter<=counter+1;
else
counter<=0;
end if;
elsif(counter<(n+1)/2)then
cout<='0';
counter<=counter+1;
elsif(counter<n) then
cout<='1';
counter<=counter+1;
else
counter<=0;
end if;
end if;
end process;
end rtl;