Question

关于VHDL语言中case语句的问题

我用case语句中完成一个简单的延迟功能，大约是4个周期，可是当我用
if count = 4 then
count <= 0;
next_state <= C;
else
count <= count + 1;
next_state <= B;
end if;
这个语句实现时，编译虽然通过，可是仿真，总是一直停在这里循环，去掉这段则一切正常，想了很长时间不知道逻辑错在哪里，求救于各位牛人！！帮忙啊！！！
较详细代码见下
entity lcd is
Port ( res :in std_logic;
r1 : in std_logic;
count1 : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
lcd_en : out STD_LOGIC;
lcd_rs : out STD_LOGIC;
lcd_rw : out STD_LOGIC;
output : out STD_LOGIC_VECTOR (3 downto 0));
end lcd;
architecture Behavioral of lcd is
type my_state is(A,B,C,D);
signal state,next_state : my_state;
signal count: integer range 0 to 4:=0;
begin
lcd_en <= clk;
lcd_rw<='0';
process(clk,res)
begin
if res='1' then
state<=A;
elsif rising_edge (clk) then
state <= next_state;
end if;
end process;
process(state,next_state)
begin
lcd_rs<='0';
case (state) is
when A=>
output<="0011";
next_state<=B;
when B=>
if count = 4 then
count <= 0;
next_state <= C;
else
count <= count + 1;
next_state <= B;
end if;
when C=>
output<="0011";
next_state<=D;
.......

本程序是为了FPGA板上LCD的驱动。

望指教

Answer 1

when others=>next_state<=a;