Question

急求verilog设计八路彩灯控制器程序

下图是彩灯等的具体亮灭

Answer 1

// modelsim testbench

// 有疑问,可联系我,百度hi不方便,可以Q

module led_tb(clk,n_reset,led);

output       clk;

output       n_reset;

output [7:0] led;

reg          clk;

reg          n_reset;

led_ctrl led_inst(clk,n_reset,led);

initial

begin

        n_reset  = 1'b1;

  #20   n_reset  = 1'b0;

  #60   n_reset  = 1'b1;

end

initial

begin

  clk            = 1'b0;

  forever

    #10 clk      = ~clk;

end

endmodule

module led_ctrl(clk,n_reset,led);

input        clk;

input        n_reset;

output [7:0] led;

reg    [7:0] led;

reg    [5:0] state;

reg          next_bit;

always @(negedge n_reset,posedge clk)

if (~n_reset)

  state               <= 6'd0;

else

  state               <= state==6'd32 ? 6'd0 : state+6'd1;

always @(negedge n_reset,posedge clk)

if (~n_reset)

  led                 <= 8'h7f;

else

  if (state==6'd24)

    led               <= 8'h01;

  else if (state==6'd32)

    led               <= 8'h7f;

  else

    led               <= {led[6:0],next_bit};

always @(negedge n_reset,posedge clk)

if (~n_reset)

  next_bit            <= 1'b0;

else

  if      (state>=6'd0  && state<6'd8 )

    next_bit          <= 1'b1;

  else if (state>=6'd8  && state<6'd16)

    next_bit          <= 1'b0;

  else if (state>=6'd16 && state<6'd24)

    next_bit          <= 1'b1;

  else if (state>=6'd24 && state<6'd31)

    next_bit          <= 1'b0;

  else if (state==6'd31)

    next_bit          <= 1'b1;

  else if (state==6'd32)

    next_bit          <= 1'b0;

endmodule