跪求一个交通灯控制器的verilog代码
要求:1.东西方向为主干道,南北方向为副干道;2.主干道通行40秒后,若副干道无车,仍主干道通行,否则转换;3.换向时要有4秒的黄灯期;4.南北通行时间为20秒,到时间则...
要求:
1. 东西方向为主干道,南北方向为副干道;
2. 主干道通行40秒后,若副干道无车,仍主干道通行,否则转换;
3. 换向时要有4秒的黄灯期;
4. 南北通行时间为20秒,到时间则转换,若未到时南北方向已无车,也要转换。
5. 用数码管显示计时 展开
1. 东西方向为主干道,南北方向为副干道;
2. 主干道通行40秒后,若副干道无车,仍主干道通行,否则转换;
3. 换向时要有4秒的黄灯期;
4. 南北通行时间为20秒,到时间则转换,若未到时南北方向已无车,也要转换。
5. 用数码管显示计时 展开
2个回答
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module traffic (clock, reset, sensor1, sensor2,
red1, yellow1, green1, red2, yellow2, green2);
input clock, reset, sensor1, sensor2;
output red1, yellow1, green1, red2, yellow2, green2;
// Define the states
parameter st0 = 0, st1 = 1, st2 = 2, st3 = 3,
st4 = 4, st5 = 5, st6 = 6, st7 = 7;
reg [2:0] state, nxstate ;
reg red1, yellow1, green1, red2, yellow2, green2;
// state update
always @(posedge clock or posedge reset)
begin
if (reset)
state = st0 ;
else
state = nxstate;
end
// Calculate the next state and the outputs,
always @(state or sensor1 or sensor2)
begin
red1 = 1'b0; yellow1 = 1'b0; green1 = 1'b0;
red2 = 1'b0; yellow2 = 1'b0; green2 = 1'b0;
case (state)
st0: begin
green1 = 1'b1;
red2 = 1'b1;
if (sensor2 == sensor1)
nxstate = st1;
else if (~sensor1 & sensor2)
nxstate = st2;
else
nxstate = st0;
end
st1: begin
green1 = 1'b1;
red2 = 1'b1;
nxstate = st2;
end
st2: begin
green1 = 1'b1;
red2 = 1'b1;
nxstate = st3;
end
st3: begin
yellow1 = 1'b1;
red2 = 1'b1;
nxstate = st4;
end
st4: begin
red1 = 1'b1;
green2 = 1'b1;
if (~sensor1 & ~sensor2)
nxstate = st5;
else if (sensor1 & ~sensor2)
nxstate = st6;
else
nxstate = st4;
end
st5: begin
red1 = 1'b1;
green2 = 1'b1;
nxstate = st6;
end
st6: begin
red1 = 1'b1;
green2 = 1'b1;
nxstate = st7;
end
st7: begin
red1 = 1'b1;
yellow2 = 1'b1;
nxstate = st0;
end
endcase
end
endmodule
red1, yellow1, green1, red2, yellow2, green2);
input clock, reset, sensor1, sensor2;
output red1, yellow1, green1, red2, yellow2, green2;
// Define the states
parameter st0 = 0, st1 = 1, st2 = 2, st3 = 3,
st4 = 4, st5 = 5, st6 = 6, st7 = 7;
reg [2:0] state, nxstate ;
reg red1, yellow1, green1, red2, yellow2, green2;
// state update
always @(posedge clock or posedge reset)
begin
if (reset)
state = st0 ;
else
state = nxstate;
end
// Calculate the next state and the outputs,
always @(state or sensor1 or sensor2)
begin
red1 = 1'b0; yellow1 = 1'b0; green1 = 1'b0;
red2 = 1'b0; yellow2 = 1'b0; green2 = 1'b0;
case (state)
st0: begin
green1 = 1'b1;
red2 = 1'b1;
if (sensor2 == sensor1)
nxstate = st1;
else if (~sensor1 & sensor2)
nxstate = st2;
else
nxstate = st0;
end
st1: begin
green1 = 1'b1;
red2 = 1'b1;
nxstate = st2;
end
st2: begin
green1 = 1'b1;
red2 = 1'b1;
nxstate = st3;
end
st3: begin
yellow1 = 1'b1;
red2 = 1'b1;
nxstate = st4;
end
st4: begin
red1 = 1'b1;
green2 = 1'b1;
if (~sensor1 & ~sensor2)
nxstate = st5;
else if (sensor1 & ~sensor2)
nxstate = st6;
else
nxstate = st4;
end
st5: begin
red1 = 1'b1;
green2 = 1'b1;
nxstate = st6;
end
st6: begin
red1 = 1'b1;
green2 = 1'b1;
nxstate = st7;
end
st7: begin
red1 = 1'b1;
yellow2 = 1'b1;
nxstate = st0;
end
endcase
end
endmodule
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