Question

求用vhdl语言做个全加器的程序

越多越好，提供的多分给的越多

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

--USE IEEE.STD_LOGIC_unsigned.ALL;
--USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY if_adder IS
PORT (a,b,c : IN STD_LOGIC;
co, so : out STD_LOGIC);
END ENTITY if_adder ;
ARCHITECTURE fh1 OF if_adder is
signal ab : STD_LOGIC_vector(1 downto 0);
BEGIN
abc<=a&b&c;
PROCESS(abc)
BEGIN
case abc is
when "000"=>so<='0';co<='0';
when "001"=>so<='1';co<='0';
when "010"=>so<='1';co<='0';
when "011"=>so<='0';co<='1';
when "100"=>so<='1';co<='0';
when "101"=>so<='0';co<='1';
when "110"=>so<='0';co<='1';
when "111"=>so<='1';co<='1';
end case;
END PROCESS;
END ARCHITECTURE fh1 ;

Answer 2

首先 我不知道你要几位全加器！！！！！
找本书 看一天 你就会了！！！！！！！！！！

Answer 3

好答案