Question

异步fifo要求用verilog编写

请设计一个异步FIFO，完成数据平滑功能，FIFO的深度为256，宽度为8位，实时给出读空和溢出指示，写时钟为带间隔的100MHz，读时钟为5MHz。
不要网上COPY的，要自己写的。 发我邮箱，wg_135721@qq.com 谢谢
注意是异步FIFO

Answer 1

module FIFO(Wr_Clk,//write FIFO clock
nWr, //write FIFO signal
Din, //write FIFO data
Rd_Clk,//read FIFO clock
nRd, //read FIFO signal
Dout, //read FIFO data

Full, // 1 = FIFO full
Empty);// 1 = FIFO empty

input Wr_Clk, nWr, Rd_Clk, nRd;
input [Bsize-1:0] Din;
output [Bsize-1:0] Dout;
output Full, Empty;

reg Full, Empty;
reg [Bsize-1:0] Buff [Dsize-1:0];
reg [Asize:0] Wr_Addr_Bin, Rd_Addr_Bin;
reg [Asize:0] Sync_Wr_Addr0_Gray, Sync_Wr_Addr1_Gray, Sync_Wr_Addr2_Gray;
reg [Asize:0] Sync_Rd_Addr0_Gray, Sync_Rd_Addr1_Gray, Sync_Rd_Addr2_Gray;

wire [Asize-1:0] FIFO_Entry_Addr, FIFO_Exit_Addr;
wire [Asize:0] Wr_NextAddr_Bin, Rd_NextAddr_Bin;
wire [Asize:0] Wr_NextAddr_Gray, Rd_NextAddr_Gray;
wire Asyn_Full, Asyn_Empty;

parameter
Dsize = 256, Asize = 8,
Bsize = 8;

initial
begin
Full = 0;
Empty = 1;

Wr_Addr_Bin = 0;
Rd_Addr_Bin = 0;

Sync_Wr_Addr0_Gray = 0;
Sync_Wr_Addr1_Gray = 0;
Sync_Wr_Addr2_Gray = 0;
Sync_Rd_Addr0_Gray = 0;
Sync_Rd_Addr1_Gray = 0;
Sync_Rd_Addr2_Gray = 0;
end
////////////////////FIFO数据的写入与输出//////////////////////////////////////
assign FIFO_Exit_Addr = Rd_Addr_Bin[Asize-1:0];
assign FIFO_Entry_Addr = Wr_Addr_Bin[Asize-1:0];

assign Dout = Buff[FIFO_Exit_Addr];
always @ (posedge Wr_Clk)
begin
if (~nWr & ~Full) Buff[FIFO_Entry_Addr] <= Din;
else Buff[FIFO_Entry_Addr] <= Buff[FIFO_Entry_Addr];
end
///////////////////FIFO读写的地址生成器///////////////////////////////////////
assign Wr_NextAddr_Bin = (~nWr&~Full) ?Wr_Addr_Bin[Asize:0]+1:Wr_Addr_Bin[Asize:0];
assign Rd_NextAddr_Bin = (~nRd&~Empty)?Rd_Addr_Bin[Asize:0]+1:Rd_Addr_Bin[Asize:0];

assign Wr_NextAddr_Gray = (Wr_NextAddr_Bin >> 1) ^ Wr_NextAddr_Bin;
assign Rd_NextAddr_Gray = (Rd_NextAddr_Bin >> 1) ^ Rd_NextAddr_Bin;

always @ (posedge Wr_Clk)
begin
Wr_Addr_Bin <= Wr_NextAddr_Bin;
Sync_Wr_Addr0_Gray <= Wr_NextAddr_Gray;
end

always @ (posedge Rd_Clk)
begin
Rd_Addr_Bin <= Rd_NextAddr_Bin;
Sync_Rd_Addr0_Gray <= Rd_NextAddr_Gray;
end
///////////////////采用双锁存器把异步信号同步起来/////////////////////////////
always @ (posedge Wr_Clk)
begin
Sync_Rd_Addr2_Gray <= Sync_Rd_Addr1_Gray;//读信号同步到写时钟
Sync_Rd_Addr1_Gray <= Sync_Rd_Addr0_Gray;
end

always @ (posedge Rd_Clk)
begin
Sync_Wr_Addr2_Gray <= Sync_Wr_Addr1_Gray;//写信号同步到读时钟
Sync_Wr_Addr1_Gray <= Sync_Wr_Addr0_Gray;
end
/////////////////将产生的Full信号和Empty信号同步的各自的时钟域上//////////////
assign Asyn_Empty = (Rd_NextAddr_Gray==Sync_Wr_Addr2_Gray);
assign Asyn_Full = (Wr_NextAddr_Gray=={~Sync_Rd_Addr2_Gray[Asize:Asize-1],
Sync_Rd_Addr2_Gray[Asize-2:0]});

always @ (posedge Wr_Clk)
begin
Full <= Asyn_Full;
end

always @ (posedge Rd_Clk)
begin
Empty <= Asyn_Empty;
end
//////////////////////////////////////////////////////////////////////////////
endmodule

Answer 2

`timescale 1ns / 100ps

`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset

module generic_fifo_sc (clk, rst, clr, din, we, dout, re,
full, empty, full_r, empty_r,
full_n, empty_n, full_n_r, empty_n_r,
level);

parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;

input clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input re;
output full, full_r;
output empty, empty_r;
output full_n, full_n_r;
output empty_n, empty_n_r;
output [1:0] level;

// Local Wires

reg [aw:0] wp;
wire [aw:0] wp_pl1;
reg [aw:0] rp;
wire [aw:0] rp_pl1;
reg full_r;
reg empty_r;
wire [aw:0] diff;
reg [aw:0] diff_r;
reg re_r, we_r;
wire full_n, empty_n;
reg full_n_r, empty_n_r;
reg [1:0] level;

// Memory Block

generic_dpram #(aw,dw) u0(
.rclk( clk ),
.rrst( !rst ),
.rce( 1'b1 ),
.oe( 1'b1 ),
.raddr( rp[aw-1:0] ),
.do( dout ),
.wclk( clk ),
.wrst( !rst ),
.wce( 1'b1 ),
.we( we ),
.waddr( wp[aw-1:0] ),
.di( din )
);

// Misc Logic

always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) wp <= #1 {aw+1{1'b0}};
else
if(clr) wp <= #1 {aw+1{1'b0}};
else
if(we) wp <= #1 wp_pl1;

assign wp_pl1 = wp + { {aw{1'b0}}, 1'b1};

always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) rp <= #1 {aw+1{1'b0}};
else
if(clr) rp <= #1 {aw+1{1'b0}};
else
if(re) rp <= #1 rp_pl1;

assign rp_pl1 = rp + { {aw{1'b0}}, 1'b1};

// Combinatorial Full & Empty Flags

assign empty = (wp == rp);
assign full = (wp[aw-1:0] == rp[aw-1:0]) & (wp[aw] != rp[aw]);

// Registered Full & Empty Flags

always @(posedge clk)
empty_r <= #1 (wp == rp) | (re & (wp == rp_pl1));

always @(posedge clk)
full_r <= #1 ((wp[aw-1:0] == rp[aw-1:0]) & (wp[aw] != rp[aw])) |
(we & (wp_pl1[aw-1:0] == rp[aw-1:0]) & (wp_pl1[aw] != rp[aw]));

// Combinatorial Full_n & Empty_n Flags

assign diff = wp-rp;
assign empty_n = diff < n;
assign full_n = !(diff < (max_size-n+1));

always @(posedge clk)
level <= #1 {2{diff[aw]}} | diff[aw-1:aw-2];

// Registered Full_n & Empty_n Flags

always @(posedge clk)
re_r <= #1 re;

always @(posedge clk)
diff_r <= #1 diff;

always @(posedge clk)
empty_n_r <= #1 (diff_r < n) | ((diff_r==n) & (re | re_r));

always @(posedge clk)
we_r <= #1 we;

always @(posedge clk)
full_n_r <= #1 (diff_r > max_size-n) | ((diff_r==max_size-n) & (we | we_r));

// Sanity Check

always @(posedge clk)
if(we & full)
$display("%m WARNING: Writing while fifo is FULL (%t)",$time);

always @(posedge clk)
if(re & empty)
$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);

endmodule

Answer 3

语法看夏宇文的书，设计fifo看verilog HDL 高级数字设计888页～