Question

用vhdl编写用D触发器设计异步四位二进制加法计数器

Answer 1

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY asy_bin_counter IS

 PORT (clock: IN STD_LOGIC;

       q_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

       carry_out: OUT STD_LOGIC);

END asy_bin_counter;

ARCHITECTURE ONE OF asy_bin_counter IS

  SIGNAL d,q: STD_LOGIC_VECTOR(3 DOWNTO 0);

  COMPONENT dff_2

    PORT (clk,d: IN STD_LOGIC;

          q,q_n: OUT STD_LOGIC);

  END COMPONENT;

BEGIN

  U0:dff_2 PORT MAP (clk => clock, d => d(0), q => q(0), q_n => d(0));

  U1:dff_2 PORT MAP (clk => q(0), d => d(1), q => q(1), q_n => d(1));

  U2:dff_2 PORT MAP (clk => q(1), d => d(2), q => q(2), q_n => d(2));

  U3:dff_2 PORT MAP (clk => q(2), d => d(3), q => q(3), q_n => d(3));

  q_out <= NOT q;

  carry_out <= NOT (q(3) OR q(2) OR q(1) OR q(0));

END ONE;