Question

verilog fft ip核多通道仿真

我在testbench文件中输入如下代码作为多通道FFT ip核的输入
always@(posedge clk) begin
i <= i + 1;
j <= j + 1;
if(start) begin
case(i)
3'b000: xn0_re <= 8'd20;
3'b001: xn0_re <= 8'd30;
3'b010: xn0_re <= 8'd40;
3'b011: xn0_re <= 8'd50;
3'b100: xn0_re <= 8'd60;
3'b101: xn0_re <= 8'd70;
3'b110: xn0_re <= 8'd80;
3'b111: xn0_re <= 8'd000;
default;
endcase
case(j)
3'b000: xn1_re <= 8'd30;
3'b001: xn1_re <= 8'd40;
3'b010: xn1_re <= 8'd50;
3'b011: xn1_re <= 8'd60;
3'b100: xn1_re <= 8'd70;
3'b101: xn1_re <= 8'd80;
3'b110: xn1_re <= 8'd90;
3'b111: xn1_re <= 8'd000;
default;
endcase
end
end
但仿真结果显示只输入了xn1_re，请问如何修改程序，可以使两组数据都输入。

Answer 1

always@(posedge clk) begin
i <= i + 1;
if(start) begin
case(i)
3'b000: xn0_re <= 8'd20;
3'b001: xn0_re <= 8'd30;
3'b010: xn0_re <= 8'd40;
3'b011: xn0_re <= 8'd50;
3'b100: xn0_re <= 8'd60;
3'b101: xn0_re <= 8'd70;
3'b110: xn0_re <= 8'd80;
3'b111: xn0_re <= 8'd000;
default;
endcase
end
end
always@(posedge clk) begin
j <= j + 1;
if(start) begin
case(j)
3'b000: xn1_re <= 8'd30;
3'b001: xn1_re <= 8'd40;
3'b010: xn1_re <= 8'd50;
3'b011: xn1_re <= 8'd60;
3'b100: xn1_re <= 8'd70;
3'b101: xn1_re <= 8'd80;
3'b110: xn1_re <= 8'd90;
3'b111: xn1_re <= 8'd000;
default;
endcase
end
end

这样试试

追问

你说的方法我也试过，效果和我的一样，也只有xn1_re输入