Question

用Verilog 编写的UART（异步收发器）发送/接收模块程序，求每一句的注释！！！

发送模块
module send(clk,clkout,Datain,TXD,TI,WR);
input WR;
input [7:0]Datain;
input clk;
output clkout;
output TXD,TI;
reg[9:0]Datainbuf,Datainbuf2;
reg WR_ctr,TI,txd_reg;
reg [3:0]bincnt;
reg [15:0] cnt;
wire clk_equ;
parameter cout=5000;

/*************/

always@(posedge clk)
begin
if(clk_equ)
cnt=16'd0;
else
cnt=cnt+1'b1;
end
assign clk_equ=(cnt==cout);
assign clkout=clk_equ;

/*************/

always@(posedge clk)
begin
if(WR)
begin
Datainbuf={1'b1,Datain[7:0],1'b0};
WR_ctr=1'b1;
end
else if(TI==0)
WR_ctr=1'b0;
end

/************/

always@(posedge clk)
begin
if(clk_equ)
begin
if(WR_ctr==1||bincnt<4'd10)
begin
if(bincnt<4'd10)
begin
txd_reg=Datainbuf2[0];
Datainbuf2=Datainbuf>>bincnt;
bincnt=bincnt+4'd1;
TI=1'b0;
end
else
bincnt=4'd0;
end
else
begin
txd_reg=1'b1;
TI=1'b1;
end
end
end
assign TXD=txd_reg;
endmodule

接收模块
module rec(clk,clkout,Dataout,RXD,RI);
input clk,RXD;
output clkout,RI;
output [7:0] Dataout;
reg StartF,RI;
reg [9:0] UartBuff;
reg [3:0]count,count_bit;
reg [15:0] cnt;
reg [2:0]bit_collect;
wire clk_equ,bit1,bit2,bit3,bit;
parameter cout=312;

/************/

always@(posedge clk)
begin
if(clk_equ)
cnt=16'd0;
else
cnt=cnt+1'b1;
end

assign clk_equ=(cnt==cout);
assign clkout=clk_equ;
assign bit1=bit_collect[0]&bit_collect[1];
assign bit2=bit_collect[1]&bit_collect[2];
assign bit3=bit_collect[0]&bit_collect[2];
assign bit=bit1|bit2|bit3;

always@(posedge clk)
begin
if(clk_equ)
begin
if(! StartF)
begin
if(! RXD)
begin
count=4'b0;
count_bit=4'b0;
RI=1'b0;
StartF=1'b1;
end
else RI=1'b1;
end
else
begin
count=count+1'b1;
if(count==4'd6)
bit_collect[0]=RXD;
if(count==4'd7)
bit_collect[1]=RXD;
if(count==4'd8)
begin
bit_collect[2]=RXD;
UartBuff[count_bit]=bit;
count_bit=count_bit+1'b1;
if((count_bit==4'd1)&&(UartBuff[0]==1'b1))
begin
StartF=1'b0;
end
RI=1'b0;
end
if(count_bit>4'd9)
begin
RI=1'b1;
StartF=1'b0;

Answer 1

每一句注释。。。这个真的这么难看懂么。。

追问

求大神帮助啊！！！时间紧迫没工夫仔细研究了