Question

这个verilog程序的问题怎么解决？

module mos1(out,a,b);
output out;
input a,b;
wire c,pwr;
supply1 vdd;
supply0 gnd;
assign pwr=vdd;
pmos p1(c,pwr,b);
pmos p2(out,c,a);
nmos n1(out,gnd,a);
nmos n2(out,gnd,b);
endmodule

综合时候显示错误
ERROR:Xst:850 - "mos1.v" line 29: Unsupported Switch or User Defined Primitive.
ERROR:Xst:850 - "mos1.v" line 30: Unsupported Switch or User Defined Primitive.
ERROR:Xst:850 - "mos1.v" line 31: Unsupported Switch or User Defined Primitive.
求指教
pmos p1(c,pwr,b);这是28行
pmos p2(out,c,a);29行
nmos n1(out,gnd,a);30行
nmos n2(out,gnd,b);31行
跪求解答

Answer 1

调用错误，举个例子给你
pmos p1(c,pwr,b);不能这样写。

pmos p1(.c (c),
.pwr(pwr),
.b(b)
); 前面要加点，前面的字母是调用程序的端口，括号里面的字母是本程序使用的端口