Question

数电作业用verilog设计延时启动

求救，急求，verilog中用计数器计数译码器译码最后数码管显示54321延时启动的具体程序，

Answer 1

供参考：
module delay(clk,rst,disp);
input clk,rst;
output reg [7:0] disp;

parameter C_FR = 32'd20_000_000; //定义系统时钟20MHz
parameter C_SEC = 4'd2; //定义每2秒一次

reg [31:0] clk_cnt;
reg [3:0] sec_cnt;

reg [3:0] dly_cnt;
reg pp1s; //秒脉冲

always@(posedge clk)//其中一向干道
if(!rst)
begin
clk_cnt <= 32'b0;
sec_cnt <= 4'b0;
pp1s <= 1'b0;
dly_cnt <= 4'd9;
end
else
begin
if (clk_cnt == C_FR)
pp1s <= 1'b1;
else
pp1s <= 1'b0;

if (pp1s)
begin
if (sec_cnt == C_SEC)
sec_cnt <= 4'b0;
else
sec_cnt <= sec_cnt + 1'b1;
end

if (pp1s && (sec_cnt == C_SEC))
dly_cnt <= dly_cnt - 1;
end

always@(*)
case (dly_cnt)
4'h0 disp = 0x3f;
4'h1 disp = 0x06;
4'h2 disp = 0x5b;
4'h3 disp = 0x4f;
4'h4 disp = 0x66;
4'h5 disp = 0x6d;
4'h6 disp = 0x7d;
4'h7 disp = 0x07;
4'h8 disp = 0x7f;
4'h9 disp = 0x6f;
default:disp = 0x3f;
endcase

endmodule