Question

verilog的基础问题

我纠结了好久，大家来帮忙看看.
LED=1是灯亮，LED=0是灯灭;

这个代码，LED全亮.
reg变量自加，a不是应该等于3吗？
之后我又做了一次改变。

结果LED2灭了,看来CASE里的语句还正常的.
之后我看了看一本VERILOG入门的书籍，上面说

于是我把代码改成了如下.

但是灯依旧是全亮，没出现我要的结果
我用的是altera
我的代码如下
module testa(LED0,LED1,LED2,LED3,LED4,LED5,LED6,LED7,KEY0,KEY1,KEY2,KEY3);
input KEY0,KEY1,KEY2,KEY3;
output LED0,LED1,LED2,LED3,LED4,LED5,LED6,LED7;
reg LED0,LED1,LED2,LED3,LED4,LED5,LED6,LED7;
reg [7:0] a=0,b=0;
always @(KEY0 )
begin
if(1) begin a<=(b+1); end
if(1) begin b<=a; end
if(1) begin a<=(b+1); end
if(1) begin b<=a; end
if(1) begin a<=(b+1); end
case(a)
8'd1: LED0=0;
8'd2: LED1=0;
8'd3: LED2=0;
8'd4: LED3=0;
8'd5: LED4=0;
8'd6: LED5=0;
8'd7: LED6=0;
default:
begin
LED0=1;
LED1=1;
LED2=1;
LED3=1;
LED4=1;
LED5=1;
LED6=1;
LED7=1;
end
endcase
if(KEY0==0)
begin
LED0=1;
LED1=1;
LED2=1;
LED3=1;
LED4=1;
LED5=1;
LED6=1;
LED7=1;
end
end
endmodule
求帮助





Answer 1

已经解决
module testa(LED0,LED1,LED2,LED3,LED4,LED5,LED6,LED7,clk,rst);
//input KEY0,KEY1,KEY2,KEY3;
input clk;
input rst;
output LED0,LED1,LED2,LED3,LED4,LED5,LED6,LED7;
reg LED0,LED1,LED2,LED3,LED4,LED5,LED6,LED7;
reg [7:0] a;
always @(posedge clk )
begin
if(!rst)
a<=0;
else
begin
if(a==3)
a<=3;
else
a<=a+1;
end
case(a)
8'd1: LED0<=0;
8'd2: LED1<=0;
8'd3: LED2<=0;
8'd4: LED3<=0;
8'd5: LED4<=0;
8'd6: LED5<=0;
8'd7: LED6<=0;
8'd8: LED7<=0;
default:
begin
LED0<=1;
LED1<=1;
LED2<=1;
LED3<=1;
LED4<=1;
LED5<=1;
LED6<=1;
LED7<=1;
end
endcase
end
endmodule