Question

VHDL语言错误

library ieee;
use ieee.std_logic_1164.all;
entity h_sub8 is
port ( m1,m2,m3,m4,m5,m6,m7,m8: in std_logic;
n1,n2,n3,n4,n5,n6,n7,n8: in std_logic;
h1,h2,h3,h4,h5,h6,h7,h8: out std_logic);
end;
architecture one of h_sub8 is
component h_sub
port (x1,y1,sub_in: in std_logic;
diffr,sub_out: out std_logic);
end component;
signal a,b,c,d,e,f,g: std_logic;
begin
u1: h_sub port map(x1=>m1,y1=>n1,diffr=>h1,sub_in<='0',sub_out=>a);
u2: h_sub port map(x1=>m2,y1=>n2,diffr=>h2,sub_in=>a,sub_out=>b);
u3: h_sub port map(x1=>m3,y1=>n3,diffr=>h3,sub_in=>b,sub_out=>c);
u4: h_sub port map(x1=>m4,y1=>n4,diffr=>h4,sub_in=>c,sub_out=>d);
u5: h_sub port map(x1=>m5,y1=>n5,diffr=>h5,sub_in=>d,sub_out=>e);
u6: h_sub port map(x1=>m6,y1=>n6,diffr=>h6,sub_in=>e,sub_out=>f);
u7: h_sub port map(x1=>m7,y1=>n7,diffr=>h7,sub_in=>f,sub_out=>g);
u8: h_sub port map(x1=>m8,y1=>n8,diffr=>h8,sub_in=>g,sub_out<='0');
end;

错误：Error (10437): VHDL Association List error at eda3-4-2.vhd(15): positional associations must be listed before named associations

求解答！

Answer 1

将u1: h_sub port map(x1=>m1,y1=>n1,diffr=>h1,sub_in<='0',sub_out=>a);改成
GND <= '0';
u1: h_sub port map(x1=>m1,y1=>n1,diffr=>h1,sub_in=>GND,sub_out=>a);
当然，需要在结构体的一开始增加一个信号声明，信号名称叫做GND。例如
signal a,b,c,d,e,f,g,GND: std_logic;