Question

Verilog 存储器输出总是编译报错?有那位专家帮我指导小弟一下？

Quartus II 错误提示如下：Error (10137): Verilog HDL Procedural Assignment error at communication.v(43): object "special_data" on left-hand side of assignment must have a variable data type

/*
*
* File name: communiction.v
* File description: PC with CPLD send and receive data frame to execute funtion
* Operating environment: QUARTUS II 9.0,MaxII EPM1270T144C5N
*
* This version: 1.0
* Author: wangdaojin(wangdaojin98462@163.com)
* Previous Author: none
* Complete date:
*
*/
module comunication (
input DS,
input[7:0] UsbData,
output[7:0] special_data,
output[7:0] function_data,
output[7:0] address_data,
output[7:0] operation_data1,
output[7:0] operation_data2,
output[7:0] operation_data3,
output[7:0] operation_data4,
output[7:0] operation_data5
);
reg startCnt;
reg[3:0] ReceiveCount;
reg[7:0] mem1[3:0];

always @ (negedge DS) begin
if(ReceiveCount <= 4'h07)
begin
mem1[ReceiveCount]<= UsbData[7:0];
ReceiveCount <= ReceiveCount+1;
end
else
begin
if(ReceiveCount == 4'h07)
begin
startCnt <= 1'b1;
ReceiveCount <= 4'h00;
special_data <= mem1[0];
end
else ReceiveCount <= 4'h00;
end
end

always @ (posedge startCnt)
begin
function_data <= mem1[1];
address_data <= mem1[2];
operation_data1 <= mem1[3];
operation_data2 <= mem1[4];
operation_data3 <= mem1[5];
operation_data4 <= mem1[6];
operation_data5 <= mem1[7];

startCnt <= 1'b0;
end

endmodule

Answer 1

special_data 定义时再加个reg啊，
写句reg [7:0] special_data；就行了。。