Question

基于FPGA的VGA设计

module vga(rst_n, clock, hsyn, vsyn, red, green, blue);
input rst_n;
input clock;

output hsyn;
output vsyn;
output red;
output green;
output blue;

reg hsyn;
reg vsyn;
reg red;
reg green;
reg blue;

//临时变量
reg vga_hsyn;
reg vga_vsyn;
reg vga_red;
reg vga_green;
reg vga_blue;
reg [9:0]x_cnt;
reg [9:0]y_cnt;
reg clk1;
reg clk2;

always @(posedge clock, negedge rst_n)
begin
if(!rst_n)
clk1 = 0;
else if(clock)
if (clk1 == 10'd)
clk1 = 0 ;
else
clk1 = clk1 + 1;

end

always @(posedge clock, negedge rst_n)
begin
if(!rst_n)
clk2 = 0;
else if(clock)
if (clk2 == 10'd1588)
clk2 = 0 ;
else
clk2= clk2 + 1;

end
//x_cnt
always @(posedge clk2, negedge rst_n)
begin
if(!rst_n)
x_cnt <= 0;
else
begin
if(x_cnt == 10'd799)
x_cnt <= 0;
else
x_cnt <= x_cnt + 1;
end

end

//y_cnt
always @(posedge clk1, negedge rst_n)
begin
if(!rst_n)
y_cnt <= 0;
else
begin
if(x_cnt == 10'd799)
begin
if(y_cnt == 10'd482)
y_cnt <= 0;
end
else
y_cnt <= y_cnt + 1;
end
end

//vga_hsyn
always @(posedge clock, negedge rst_n)
begin
if(!rst_n)
vga_hsyn <= 0;
else
if(x_cnt < 10'd640)
vga_hsyn <= 1'b1;
else
vga_hsyn <= 0;
end

//vga_vsyn
always @(posedge clock, negedge rst_n)
begin
if(!rst_n)
vga_vsyn <= 0;
else
if(y_cnt < 10'd480)
vga_vsyn <= 1'b1;
else
vga_vsyn <= 0;
end

//hsyn,vsyn
always @(posedge clock, negedge rst_n)
begin
if(!rst_n)
begin
hsyn <=0;
vsyn <=0;
end
else
begin
hsyn <= x_cnt <= 10'd50;
vsyn <= y_cnt <= 10'd6;
end
end

//red
always @(posedge clock, negedge rst_n)
begin
if(!rst_n)
red <= 0;
else
red <= (vga_red && vga_hsyn && vga_vsyn);
end

//green
always @(posedge clock, negedge rst_n)
begin
if (!rst_n)
green <= 0;
else
green <= (vga_green && vga_hsyn && vga_vsyn);
end

//blue
always @(posedge clock, negedge rst_n)
begin
if(!rst_n)
blue <= 0;
else
blue <= (vga_blue && vga_hsyn && vga_vsyn);
end

always @(posedge clock, negedge rst_n)
begin
if(!rst_n)
begin
vga_red <= 0;
vga_green <= 0;
vga_blue <= 0;
end
else
begin
if (x_cnt > 10'd10 && x_cnt < 10'd120)
begin
vga_red <= 1'b1;
vga_green <= 0;
vga_blue <= 0;
end
else if (x_cnt >10'd120 && x_cnt < 10'd240)
begin
vga_red <= 0;
vga_green <= 1'b1;
vga_blue <= 0;
end
else if(x_cnt > 10'd240 && x_cnt < 10'd360)
begin
vga_red <= 0;
vga_green <= 0;
vga_blue <= 1'b1;
end
else if(x_cnt > 10'd360 && x_cnt < 10'd480)
begin
vga_red <= 1'b1;
vga_green <= 1'b1;
vga_blue <= 0;
end
else
begin
vga_red <= 0;
vga_green <= 0;
vga_blue <= 0;
end
end
end
endmodule
请问最后显示什么图像？最好解释一下大概意思，谢啦
我说那位沙发，干你丫，明白人几眼就看出个大概了，还用的着你吗

Answer 1

这个显示的是网格状的
有暗红色 白色 黑色 等
像80年代的床单 哈哈

Answer 2

我干，都是穷鬼！
给个200分我就给你看了。

Answer 3

程序我写过，关键看定义的RGB三种颜色的具体2进制表示了，呵呵