Question

Modelsim仿真出现的问题，求助大家！！

程序和错误如下：
`timescale 1 ps/ 1 ps
module muxtwo_vlg_tst();
reg a;
reg b;
reg sl;
wire out;
muxtwo i1 (
.a(a),
.b(b),
.out(out),
.sl(sl)
);
initial
begin
a=1;
b=0;
sl=0;
#100 $finish;
end
always
begin
#2 sl=~sl;
#5 a=~a;
#3 b=~b;
end
endmodule

# vsim work.muxtwo_vlg_tst
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: E:/FPGA_Study/modelsim/3/muxtwo_vlg_tst.v(18): Module 'muxtwo' is not defined.
# Optimization failed
# Error loading design

Answer 1

很明显错误的是Error:E:/FPGA_Study/modelsim/3/muxtwo_vlg_tst.v(18): Module 'muxtwo' is not defined.

也就是muxtwo这个模块没定义，你的这个模块的.v文件添加到modelsim工程里了吗？