Question

verilog程序问题，还是quartus的问题？？

今天我尝试在quartus中进行综合。所以我从书中抄了下面的verilog代码（很简单，很基础），(项目和文件名都为fre_ctr)：

module fre_ctr(rst,clk,load,count_en,count_clr);
output count_en,count_clr,load;
input rst,clk;
reg count_clr,load;
always @(posedge clk)
begin if(rst) begin count_en <= 0; load <= 1; end
else begin count_en <= ~count_en;
load <= ~count_en;
end
end
assign count_clr = ~clk&load;
endmodule

但编译出错：
Error (10137): Verilog HDL Procedural Assignment error at fre_ctr.v(6): object "count_en" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at fre_ctr.v(7): object "count_en" on left-hand side of assignment must have a variable data type
Error (10219): Verilog HDL Continuous Assignment error at fre_ctr.v(11): object "count_clr" on left-hand side of assignment must have a net type

我不知道我的代码错在哪里？希望大家指点！！
谢

Answer 1

呵呵
object "count_clr" on left-hand side of assignment must have a net type
这个意思是assign语句只能对wire型变量赋值
Error (10137): Verilog HDL Procedural Assignment error at fre_ctr.v(6): object "count_en" on left-hand side of assignment must have a variable data type
在always块语句里只能是reg型变量赋值
问题就是这两点~~
你还是就看看书吧

Answer 2

你程序中的第四行：
reg count_clr,load;
应该改成
reg count_en,load;

always块里面对信号赋值，信号类型一定要是reg型；
always块外用assign语句对型号赋值，信号类型一定是wire型；

你程序中把count_clr 这个output变量声明成了reg型，导致第三个error；
没有把count_en声明称reg，导致了第一二个error；

另外，output的缺省为wire型

Answer 3

以上代码有很明显的两点错误，不在quartus。

1，object "count_clr" on left-hand side of assignment must have a net type

这个意思是assign语句只能对wire型变量赋值。

2，Error (10137): Verilog HDL Procedural Assignment error at fre_ctr.v(6): object "count_en" on left-hand side of assignment must have a variable data type
在always块语句里只能是reg型变量赋值。

Answer 4

reg count_clr,load;
这句话要改为
wire count_clr;
reg load;

对于reg型变量不可以用assign语句进行赋值，好好看看书，朋友