Question

VHDL设计的储存模块用QuartusII验证出现Error: Cannot synthesize initialized RAM logic "RAM1"怎么办

这个模块的功能是存储数据，取字(lw)和存字(sw)指令中使用得到数据存储器，
下面是代码：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Datememory is
port( addr : in std_logic_vector(31 downto 0);
writedate : in std_logic_vector(31 downto 0);
MemWrite,MemRead : in std_logic;
Readdate : out std_logic_vector(31 downto 0));
end Datememory;

architecture Behavioral of Datememory is
type RAMtype is array (0 to 127) of std_logic_vector(31 downto 0);
signal RAM1: RAMtype:=(others=>(others=>'0')); --初始化所有的寄存器为0
begin
process(MemWrite,MemRead,Writedate,addr,RAM1)
begin

if MemWrite='1' then --写有效的时候
RAM1(CONV_INTEGER(addr(6 downto 0))) <= Writedate;
elsif MemRead='1' then --读有效的时候
Readdate <= RAM1(CONV_INTEGER(addr(6 downto 0)));
else Readdate <= (others=>'0'); --其他情况输出
end if;

end process;

end Behavioral;

Answer 1

Quartus不支持对这种初始化方式的代码进行综合
可以用$readmemb或$readmemh完成ram的初始化（9.0以上版本支持这种方式的综合）
例如
module ram_with_init(
output reg [7:0] q,
input [7:0] d,
input [4:0] write_address, read_address,
input we, clk
);
reg [7:0] mem [0:31];

integer i;

initial begin
for (i = 0; i < 32; i = i + 1)
mem[i] = i[7:0];
end

always @ (posedge clk)
begin
if (we)
mem[write_address] <= d;
q <= mem[read_address];
end
endmodule

初始值也可以通过文件指定
initial
begin
$readmemb("ram.txt", mem);
end

追问

看不懂你写的这个是什么，但是刚才我把源代码中：
type RAMtype is array (0 to 127) of std_logic_vector(31 downto 0);

改成：
type RAMtype is array (127 to 0) of std_logic_vector(31 downto 0);

就编译成功了
不理解这其中的原因，继续等待热心人答案，还是先谢谢您的解答

追答

我这里的例子是verilog的
vhdl的ram初始化功能较弱 不支持从文件读取
你说的把0 to 127改成127 to 0能编译挺奇怪的 应该是127 downto 0才对
而且0 to 127是肯定正确的 Quartus的官方文档上都这么写的
你可以看下Quartus的Recommended HDL Coding Styles给出的例子
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY ram_with_init IS
PORT(
clock: IN STD_LOGIC;
data: IN UNSIGNED (7 DOWNTO 0);
write_address: IN integer RANGE 0 to 31;
read_address: IN integer RANGE 0 to 31;
we: IN std_logic;
q: OUT UNSIGNED (7 DOWNTO 0));
END;
ARCHITECTURE rtl OF ram_with_init IS
TYPE MEM IS ARRAY(31 DOWNTO 0) OF unsigned(7 DOWNTO 0);
FUNCTION initialize_ram
return MEM is
variable result : MEM;
BEGIN
FOR i IN 31 DOWNTO 0 LOOP
result(i) := to_unsigned(natural(i), natural'(8));
END LOOP;
RETURN result;
END initialize_ram;
SIGNAL ram_block : MEM := initialize_ram;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
q <= ram_block(read_address);
END IF;
END PROCESS;
END rtl;

Answer 2

兄弟你知道为什么不行了吗？ 我也遇到这个问题了，但是在resgiter file里我用的相同的方法那就可以跑