Question

Verilog语言写的一个小程序出错，在ISE软件中，大概实现一个跑马灯

ERROR:HDLCompiler:806 - "D:/StudyProgram/ISE/14.7/Design_Test/Test_2.3/digt_Module.v" Line 30: Syntax error near "=".
ERROR:HDLCompiler:806 - "D:/StudyProgram/ISE/14.7/Design_Test/Test_2.3/digt_Module.v" Line 33: Syntax error near "always".
ERROR:HDLCompiler:806 - "D:/StudyProgram/ISE/14.7/Design_Test/Test_2.3/digt_Module.v" Line 45: Syntax error near "always".
ERROR:HDLCompiler:806 - "D:/StudyProgram/ISE/14.7/Design_Test/Test_2.3/digt_Module.v" Line 59: Syntax error near "always".
ERROR:HDLCompiler:806 - "D:/StudyProgram/ISE/14.7/Design_Test/Test_2.3/digt_Module.v" Line 73: Syntax error near "always".
ERROR:HDLCompiler:806 - "D:/StudyProgram/ISE/14.7/Design_Test/Test_2.3/digt_Module.v" Line 87: Syntax error near "always".
ERROR:HDLCompiler:1059 - "D:/StudyProgram/ISE/14.7/Design_Test/Test_2.3/digt_Module.v" Line 30: i is an unknown type
ERROR:HDLCompiler:598 - "D:/StudyProgram/ISE/14.7/Design_Test/Test_2.3/digt_Module.v" Line 21: Module <digt_Module> ignored due to previous errors.
这是错误~~~~~~~~
下面是主要代码：：：：
module digt_Module(
switch,clk,led1,led2,led3,led4,key
);
input switch,clk,key;
output led1,led2,led3,led4;

reg led1,led2,led3,led4;
reg[31:0] count;//计数器
reg[2:0] i;
i=1;
always@(key)
begin
always@(posedge clk)
begin
if((switch == 0)|(count == 10000000))
begin
count <= 0;
i<=i+1;
end
else
count <= count + 1;
end

always@(posedge clk)
begin
if(switch == 0)
led1 <= 0;
else
if(count == 10000000&&i==1)
begin
led1 <= ~led1;
led4 <= 0;
end
else
led1 <= led1;
end

always@(posedge clk)
begin
if(switch == 0)
led2 <= 0;
else
if(count == 10000000&&i==2)
begin
led2 <= ~led2;
led1 <= 0;
end
else
led2 <= led2;
end

always@(posedge clk)
begin
if(switch == 0)
led3 <= 0;
else
if(count == 10000000&&i==3)
begin
led3 <= ~led3;
led2 <= 0;
end
else
led3 <= led3;
end

always@(posedge clk)
begin
if(switch == 0)
led4 <= 0;
else
if(count == 10000000&&i==4)
begin
led4<= ~led4;
led3 <= 0;
i <= 1;
end
else
led4 <= led4;
end
end
endmodule

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Answer 1

always 里面还套always？