Question

VHDL语言编抢答器 四人抢答器

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity QDQ4R is
port(sta:in std_logic;
clk :in std_logic;
rst :in std_logic;
a,b,c,d :in std_logic;
lb :out std_logic;
t_limit :out std_logic_vector(3 downto 0);
led :out std_logic_vector(3 downto 0);
seg :out std_logic_vector(3 downto 0));

end QDQ4R;
architecture bhe of QDQ4R is
signal tem :std_logic_vector(3 downto 0);
signal scq :std_logic;
signal s :std_logic;
signal t :std_logic;
signal ns :std_logic;
signal s_sta :std_logic;
constant w1 :std_logic_vector:="0001";
constant w2 :std_logic_vector:="0010";
constant w3 :std_logic_vector:="0011";
constant w4 :std_logic_vector:="0100";
begin
tem<=d&c&b&a;
s<=a or b or c or d;
ns<=not(a or b or c or d);
p1: process(sta,ns)
begin
if sta='1' then
s_sta<='1';
elsif(ns'event and ns='1')then
s_sta<='0';
end if;
end process p1;
p2: process(rst,s_sta,s,t)
begin
if rst='1' then
led<="0000";
elsif(s'event and s='1')then
if (s_sta='1' and t='1') then
case tem is
when "0001"=> led<="0001";
when "0010"=> led<="0010";
when "0100"=> led<="0100";
when "1000"=> led<="1000";
when others=> led<="0000";
end case;
end if;
end if;
end process p2;

p3: process(clk,s_sta)
variable lb_cnt :std_logic_vector(1 downto 0):="10";
begin
if(s='1') then
if (clk='1' and clk'event) then
if lb_cnt>"00" then
lb<=clk;
lb_cnt:=lb_cnt+1;
else
lb_cnt:="10";
lb<='0';
end if;
end if;
end if;
end process p3;
p4: process(s)
begin
if(rst='1') then
seg<="0000";
elsif(s'event and s='1') then
case tem is
when "0001" =>seg<=w1;
when "0010" =>seg<=w2;
when "0100" =>seg<=w3;
when "1000" =>seg<=w4;
when others =>seg<="0000";
end case;
end if;
end process p4;
p5: process(clk,s_sta)
variable s_time :std_logic_vector(3 downto 0):="1010";
begin
if(clk'event and clk='1') then
if(sta='1' and s_time>"0000") then
t<='1';
s_time:=s_time-1;
t_limit<=s_time;
else
s_time:="1010";
t<='0';
end if;
end if;
end process p5;
end bhe;