Question

用verilog写了一个智能小车循迹模块 能不能有大神帮忙看一下，急求，谢谢！现在没有财富值，多谢多谢

写了一个智能小车的循迹模块总是报错
[HDL 9-806] Syntax error near "end". ["I:/vavido/project_c/project_c.srcs/sources_1/imports/new/xunji.v":101]
[HDL 9-806] Syntax error near "end". ["I:/vavido/project_c/project_c.srcs/sources_1/imports/new/xunji.v":132]
能不能有大神帮忙看一下，急求，谢谢谢谢谢谢
module xunji(
input clk,clr,
input in1,in2,in3,in4,//分别代表传感器的输入信号，依次为左一左二右一右二
//output en1,en2,//电机使能
output out11,//正转反转
output out12,
output out21,
output out22,
output reg [7:0]d1,//控制pwm信号，不能超过100
output reg [7:0]d2
);
assign inf0=(!in1)&in3&in4;
assign inf1=in1&in2&(!in4);
assign inf=!(in1&in2&in3&in4);
reg[4:0] present,next;
parameter [4:0]
idle=5'b00001, //慢速前进,初始化
fl000=5'b00010, //前进
f100=5'b00100, //后退，输入信号为0000
fl0=5'b01000, //左转，输入信号：0x11
f1=5'b10000; //右转，输入信号：11x0

always @(posedge clk or negedge clr)
begin
if(clr==1'b0) present<=idle;
else present<=next;
end

always @(present or in1 or in2 or in3 or in4)
begin
next<=idle;
case(present)
idle:
begin
if(clr==1'b0) next<= idle;
else if(inf0)
next <= fl;
else if(inf1) next<=fl0;
else if(inf2) next<=fl00;
else next<=f1000;
end
fl000:
begin
if(clr==1'b0) next<=idle;
else if(inf0)
next<=fl;
else if(inf1) next<=fl0;
else if(inf2) next<=fl00;
else next<=fl000;
end
fl00:
begin
if(clr==1'b0) next<=idle;
else if(inf0)
next<=fl;
else if(inf1) next<=fl0;
else if(inf2) next<=fl00;
else next<=fl000;
end
fl0:
begin
if(clr==1'b0) next<=idle;
else if(inf0)
next<=fl;
else if(inf1) next<=fl0;
else if(inf2) next<=fl00;
else next<=fl000;
end
f1:
begin
if(clr==1'b0) next<=idle;
else if(inf0)
next<=fl;
else if(inf1) next<=fl0;
else if(inf2) next<=fl00;
else next<=fl000;
end
default: next<=idle;
end case
end

always @(posedge clk or negedge clr)
begin
next<=idle;
case(next)
idle:
begin
out11=0;out12=1'b1; out21=1'b0;out22=1'b1;d1=10;d2=10;
end
f1000:
begin
out11=1'b0;out12=1'b1; out21=1'b0;out22=1'b1;d1=45;d2=45;
end
f100:
begin
out11=1'b1;out12=1'b0; out21=1'b1;out22=1'b0;d1=30;d2=30;
end
fl0:
begin
out11=1'b0;out12=1'b1; out21=1'b0;out22=1'b1;d1=25;d2=20;
end
fl:
begin
out11=1'b0;out12=1'b1; out21=1'b0;out22=1'b1; d1=20;d2=25;
end
default:
begin
out11=1'b0;out12=1'b1; out21=1'b0;out22=1'b1;d1=10;d2=10;
end
end case

end

endmodule

Answer 1

不用看了，自己检查格式，每个begin对应一个END case 对应一个endcase 逐一检查你就知道错在哪了。代码习惯不好造成的。

追问

刚才的改过来了，现在出现这个问题怎么改，输出是reg但主模块是wire，最好有代码，万分感谢！

[Synth 8-1852] concurrent assignment to a non-net pwm1 is not permitted ["I:/vavido/project_c/project_c.srcs/sources_1/imports/new/pwm_1.v":43]

追答

assign部分写到output后面那里试试。
另外这种复杂语句的可读性差，可以写成x<=d1*1000 if x 判断 然后给PWM1和2进行赋值。
问题原因应该是PWM1和2都是寄存器，用assign去描述综合不出电路来。