交通灯控制电路,要求红灯状态60秒,绿灯状态55秒,黄灯状态5秒 ,用verilog语言
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给一个参考的程序(出自王金明:《Verilog HDL 程序设计教程》):
语句间隔自己调整下。
//module traffic.v
/*
信号定义与说明:
CLK : 为同步时钟;
EN : 使能信号,为1的话,则控制器开始工作;
LAMPA : 控制A方向四盏灯的亮灭;其中,LAMPA0~LAMPA3,分别控制A方向的
左拐灯、绿灯、黄灯和红灯;
LAMPB : 控制B方向四盏灯的亮灭;其中,LAMPB0~LAMPB3,分别控制B方向的
左拐灯、绿灯、黄灯和红灯;
ACOUNT : 用于A方向灯的时间显示,8位,可驱动两个数码管;
BCOUNT : 用于B方向灯的时间显示,8位,可驱动两个数码管。
*/
module traffic(CLK,EN,LAMPA,LAMPB,ACOUNT,BCOUNT);
output [7:0] ACOUNT,BCOUNT;
output [3:0] LAMPA,LAMPB;
input CLK,EN;
reg [7:0] numa,numb;
reg tempa,tempb;
reg [2:0] counta,countb;
reg [7:0] aleft,agreen,ayellow,ared;
reg [7:0] bleft,bgreen,byellow,bred;
reg [3:0] LAMPA,LAMPB;
always @ (EN)
if(!EN)
begin
ared <= 8'd55;
ayellow <= 8'd5;
agreen <= 8'd40;
aleft <= 8'd15;
bred <= 8'd65;
byellow <= 8'd5;
bleft <= 8'd15;
bgreen <= 8'd30;
end
assign ACOUNT = numa;
assign BCOUNT = numb;
always @ (posedge CLK)
begin
if(EN)
begin
if(!tempa)
begin
tempa<=1'b1;
case(counta)
0: begin numa<=agreen; LAMPA<=4'd2; counta<=3'd1; end
1: begin numa<=ayellow; LAMPA<=4'd4; counta<=3'd2; end
2: begin numa<=aleft; LAMPA<=4'd1; counta<=3'd3; end
3: begin numa<=ayellow; LAMPA<=4'd4; counta<=3'd4; end
4: begin numa<=ared; LAMPA<=4'd8; counta<=3'd0; end
default: LAMPA<=4'd8;
endcase
end
else
begin
if(numa>1)
if(numa[3:0]==4'd0) begin
numa[3:0]<=4'hf;
numa[7:4]<=numa[7:4]-1'b1;
end
else numa[3:0]<=numa[3:0]-1'b1;
if(numa==2) tempa<=1'b0;
end
end
else
begin
LAMPA <=4'd8;
counta<=3'd0;
tempa <=1'b0;
end
end
always @ (posedge CLK)
begin
if(EN)
begin
if(!tempb)
begin
tempb<=1;
case(countb)
0: begin numb<=bred; LAMPB<=4'd8;countb<=3'd1; end
1: begin numb<=bgreen; LAMPB<=4'd2;countb<=3'd2; end
2: begin numb<=byellow;LAMPB<=4'd4;countb<=3'd3; end
3: begin numb<=bleft; LAMPB<=4'd1;countb<=3'd4; end
4: begin numb<=byellow;LAMPB<=4'd4;countb<=3'b0; end
default : LAMPB<=4'd8;
endcase
end
else
begin
if(numb>1)
if(numb[3:0]==4'b0)
begin
numb[3:0]<=4'hf;
numb[7:4]<=numb[7:4]-1'b1;
end
else numb[3:0]<=numb[3:0]-1'b1;
if(numb==4'd2)
tempb<=1'b0;
end
end
else
begin
LAMPB <=4'd8;
tempb <=1'b0;
countb<=3'b0;
end
end
endmodule
语句间隔自己调整下。
//module traffic.v
/*
信号定义与说明:
CLK : 为同步时钟;
EN : 使能信号,为1的话,则控制器开始工作;
LAMPA : 控制A方向四盏灯的亮灭;其中,LAMPA0~LAMPA3,分别控制A方向的
左拐灯、绿灯、黄灯和红灯;
LAMPB : 控制B方向四盏灯的亮灭;其中,LAMPB0~LAMPB3,分别控制B方向的
左拐灯、绿灯、黄灯和红灯;
ACOUNT : 用于A方向灯的时间显示,8位,可驱动两个数码管;
BCOUNT : 用于B方向灯的时间显示,8位,可驱动两个数码管。
*/
module traffic(CLK,EN,LAMPA,LAMPB,ACOUNT,BCOUNT);
output [7:0] ACOUNT,BCOUNT;
output [3:0] LAMPA,LAMPB;
input CLK,EN;
reg [7:0] numa,numb;
reg tempa,tempb;
reg [2:0] counta,countb;
reg [7:0] aleft,agreen,ayellow,ared;
reg [7:0] bleft,bgreen,byellow,bred;
reg [3:0] LAMPA,LAMPB;
always @ (EN)
if(!EN)
begin
ared <= 8'd55;
ayellow <= 8'd5;
agreen <= 8'd40;
aleft <= 8'd15;
bred <= 8'd65;
byellow <= 8'd5;
bleft <= 8'd15;
bgreen <= 8'd30;
end
assign ACOUNT = numa;
assign BCOUNT = numb;
always @ (posedge CLK)
begin
if(EN)
begin
if(!tempa)
begin
tempa<=1'b1;
case(counta)
0: begin numa<=agreen; LAMPA<=4'd2; counta<=3'd1; end
1: begin numa<=ayellow; LAMPA<=4'd4; counta<=3'd2; end
2: begin numa<=aleft; LAMPA<=4'd1; counta<=3'd3; end
3: begin numa<=ayellow; LAMPA<=4'd4; counta<=3'd4; end
4: begin numa<=ared; LAMPA<=4'd8; counta<=3'd0; end
default: LAMPA<=4'd8;
endcase
end
else
begin
if(numa>1)
if(numa[3:0]==4'd0) begin
numa[3:0]<=4'hf;
numa[7:4]<=numa[7:4]-1'b1;
end
else numa[3:0]<=numa[3:0]-1'b1;
if(numa==2) tempa<=1'b0;
end
end
else
begin
LAMPA <=4'd8;
counta<=3'd0;
tempa <=1'b0;
end
end
always @ (posedge CLK)
begin
if(EN)
begin
if(!tempb)
begin
tempb<=1;
case(countb)
0: begin numb<=bred; LAMPB<=4'd8;countb<=3'd1; end
1: begin numb<=bgreen; LAMPB<=4'd2;countb<=3'd2; end
2: begin numb<=byellow;LAMPB<=4'd4;countb<=3'd3; end
3: begin numb<=bleft; LAMPB<=4'd1;countb<=3'd4; end
4: begin numb<=byellow;LAMPB<=4'd4;countb<=3'b0; end
default : LAMPB<=4'd8;
endcase
end
else
begin
if(numb>1)
if(numb[3:0]==4'b0)
begin
numb[3:0]<=4'hf;
numb[7:4]<=numb[7:4]-1'b1;
end
else numb[3:0]<=numb[3:0]-1'b1;
if(numb==4'd2)
tempb<=1'b0;
end
end
else
begin
LAMPB <=4'd8;
tempb <=1'b0;
countb<=3'b0;
end
end
endmodule
参考资料: 王金明:《Verilog HDL 程序设计教程》
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