Question

用VHDL对负边沿触发J—K触发器进行性能描述。该触发器带有异步置0、置1输入端，低电平有效。。。

Answer 1

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY jkff IS
PORT(
clk : IN STD_logic;
rst : IN STD_logic;
st : IN STD_logic;

J,K : IN STD_logic;
Q : OUT STD_LOGIC
);
END jkff;

ARCHITECTURE a OF jkff IS

signal iQ : STD_LOGIC;

BEGIN

Q <= iQ;

process(clk,rst)
begin
if (rst = '1') then
iQ <= '0';
elsif(st ='段腔1') then
iQ<= '1';
elsif (rising_edge(clk)) then
if ((J = '1') and (K = '1'腊睁)) then
iQ <= not iQ;
elsif (J = '轮燃岁1') then
iQ <= '1';
elsif (K = '1') then
iQ <= '0';
end if;
end if;
end process;

END a;

Answer 2

parseInt(oldprice)+parseInt(newprice)
请参考