Question

VHDL 编程出错了，老是报错： Erroe:Node':9.D 'missing source Erroe:Node':10.D 'missing source

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY tesst IS
PORT(clk, reset: IN STD_LOGIC;
r1,r2,g1,g2,y1,y2: OUT STD_LOGIC);
END ENTITY tesst;

ARCHITECTURE behave OF tesst IS
TYPE states IS (st0, st1, st2);
SIGNAL current_state, next_state:states;
BEGIN

com:PROCESS(clk,reset)
BEGIN
IF(reset='1')
THEN current_state<=st0;
ELSIF(clk'EVENT AND clk='1')
THEN current_state<=next_state;
END IF;
END PROCESS com;

COM1:PROCESS(current_state,clk)

BEGIN
CASE current_state IS
WHEN st0=>r1<='0';r2<='1';g1<='1';g2<='0';y1<='0';y2<='0';
WHEN st1=>r1<='1';r2<='0';g1<='0';g2<='1';y1<='0';y2<='0';
WHEN st2=>r1<='0';r2<='0';g1<='0';g2<='0';y1<='1';y2<='1';
END CASE;
END PROCESS COM1;

END ARCHITECTURE behave;

Answer 1

源代码没有出现编译错误。上述报错是在哪个环节出现的？

追问

编译的时候

追答

我将你描述的源代码放到Quartus II中试过，可以通过编译，没有出现提示错误。